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EDI -> Empty Modules

Terry2000

Hello, 

First run through EDI 12.00 and I'm having a few teething problems.

Successfully synthesised the RTL to verilog netlist but when I import the design I'm getting the following warnings (all standard cells are in the verilog netlist are listed, I've trucated the listing for the post).

I've checked the LEF and the cells are included.

 Any ideas what I'm doing wrong?

**WARN: (ENCDB-2504):    Cell OR6M2XM is instantiated in the Verilog netlist, but is not defined.
**WARN: (ENCDB-2504):   Cell OR4M1XM is instantiated in the Verilog netlist, but is not defined.
**WARN: (ENCDB-2504):   Cell NR3M1XM is instantiated in the Verilog netlist, but is not defined.
**WARN: (ENCDB-2504):   Cell AO31M2XM is instantiated in the Verilog netlist, but is not defined.
**WARN: (ENCDB-2504):   Cell DFQRM1XM is instantiated in the Verilog netlist, but is not defined.
WARN: (EMS-63):       Message <ENCDB-2504> has exceeded the default message display limit of 20.

Found empty module (OR6M2XM).
Found empty module (OR4M1XM).
Found empty module (NR3M1XM).
Found empty module (AO31M2XM).
Found empty module (DFQRM1XM).
Starting recursive module instantiation check.
No recursion found.
Term dir updated for 0 vinsts of 85 cells.
Building hierarchical netlist for Cell hlt5000_toplevel ...
*** Netlist is unique.
** info: there are 91 modules.
** info: there are 0 stdCell insts.
 

Parents

  • If you are reading in a gate level netlist then use File->Import Design form, not the Import RTL form. Give this a try from the command line:

    set conf_ioOri R0
    set defHierChar /
    set delaycal_input_transition_delay 0.1ps
    set init_assign_buffer 1
    set init_import_mode { -keepEmptyModule 1 -timerMode 1 -treatUndefinedCellAsBbox 0}
    set init_lef_file /libs/UMC/UMxxxLSCSPMVBDS_A01/lef/uxxxlscspmvbds.lef
    set init_oa_search_lib {}
    set init_top_cell toplevel
    set init_verilog r2g_output/r2g.v
    set lsgOCPGainMult 1.000000
    init_design

Reply

  • If you are reading in a gate level netlist then use File->Import Design form, not the Import RTL form. Give this a try from the command line:

    set conf_ioOri R0
    set defHierChar /
    set delaycal_input_transition_delay 0.1ps
    set init_assign_buffer 1
    set init_import_mode { -keepEmptyModule 1 -timerMode 1 -treatUndefinedCellAsBbox 0}
    set init_lef_file /libs/UMC/UMxxxLSCSPMVBDS_A01/lef/uxxxlscspmvbds.lef
    set init_oa_search_lib {}
    set init_top_cell toplevel
    set init_verilog r2g_output/r2g.v
    set lsgOCPGainMult 1.000000
    init_design

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