hInst in cadence encounter???

hInst is hierarchical instance. Usually equivalent to a hierarchical module in Verilog. Type "dbSchema hInst" for more information.

- Brian

Many Thanks brian.........

I also read  dbSchema hInst ...information

But,Can anyone tell me How in verilog module(netlist) some inst defined as hInst and why??

we can consider all hInst as Inst in .v(verilog module)???

If you have a hierarchy such as the following then U0 and instA/U1 are insts and instA is an hInst. hInsts are hierarchical modules which have insts inside them.

module top(...);

...

     modA instA(...);

     INVXL U0(...) ;

endmodule

module modA(...);

...

   BUFXL U1(...);

endmodule

 Thanks brian...