IC5141 CDL in skipping passive devices

Hello everyone, 

 I'm trying to import a CDL netlist that contains IO pads and logic into IC5141. The issue I am having is that it skips all of the passive devices within the cell. This particular cell has 3 active MOS devices, 3 diodes, and a resistor. CDL in appears to run correctly, but upon checking the schematic, only the 3 transistors are present. Below is the appropriate snippet of the CDL file, my Device Map file, and my ni.log file. I cannot see any reason for the import process to be skipping the passive devices. Please let me know if any additional information or details are needed. 

Thank you!

 P.S. I couldn't find a way to enclose the text in a code box, so please excuse the wall of text.

-----------------CDL FILE----------------------

.SUBCKT IDDBREAK VDD VSS VSSIO

*.PININFO VDD:B VSS:B VSSIO:B

RR0 VSS net40 169.876K $SUB=VDD $[RNPPO_SP] $W=500n $L=204.91u

MNM4 VDD net40 net49 VSS NA W=40e-6 L=120n M=4

MNM0 VSS VSS VDD net49 NA W=40e-6 L=120n M=12

DD2 VSSIO VSS DP 2e-11 4.2e-05 M=5

DD0 VSS VSSIO DP 2e-11 4.2e-05 M=5

DD1 VSS VDD DP 2e-11 4.2e-05 M=5

MPM0 VDD net40 VDD VDD PR W=3e-6 L=4u M=12

.ENDS

-------------------DEVICE MAP FILE-------------------------------

devMap := nfet N_11_SPHVT

propMatch := subtype NH

devMap := pfet P_11_SPHVT

propMatch := subtype PH

devMap := nfet N_25_SP

propMatch := subtype NR

devMap := pfet P_25_SP

propMatch := subtype PR

devMap := nfet N_11_SPRVT

propMatch := subtype NA

devMap := pfet P_11_SPRVT

propMatch := subtype PA

devMap := diode DIOP_SP

propMatch := subtype DP

devMap := diode DION_SP

propMatch := subtype DN

-----------------ni.log--------------------------

==========================

Subckt: IDDBREAK

==========================

Created the CV IDDBREAK->netlist_tmp.

#####################################

MOS Instance: MPM0

#####################################

...Searching for a valid mapping in the dev-map file...

        ...Bingo! Cell mapped to P_25_SP->symbol.

Now, searching for the cellview P_25_SP->symbol in ref libs...

    ...in umc65sp: Bingo! Found the master cellview: P_25_SP->symbol.

instName->'MPM0' is created.

propName->'subtype'; propVal->'PR' is created.

propName->'w'; propVal->'3E-06' is created.

propName->'l'; propVal->'4E-06' is created.

propName->'m'; propVal->'12' is created.

'D' mapped to 'D'.

The net 'VDD' of instance 'MPM0' has been connected to the terminal 'D'.

'G' mapped to 'G'.

The net 'net40' of instance 'MPM0' has been connected to the terminal 'G'.

'S' mapped to 'S'.

The net 'VDD' of instance 'MPM0' has been connected to the terminal 'S'.

'B' mapped to 'B'.

The net 'VDD' of instance 'MPM0' has been connected to the terminal 'B'.

#####################################

MOS Instance: MNM0

#####################################

...Searching for a valid mapping in the dev-map file...

        ...Bingo! Cell mapped to N_11_SPRVT->symbol.

Now, searching for the cellview N_11_SPRVT->symbol in ref libs...

    ...in umc65sp: Bingo! Found the master cellview: N_11_SPRVT->symbol.

instName->'MNM0' is created.

propName->'subtype'; propVal->'NA' is created.

propName->'w'; propVal->'4E-05' is created.

propName->'l'; propVal->'1.2E-07' is created.

propName->'m'; propVal->'12' is created.

'D' mapped to 'D'.

The net 'VSS' of instance 'MNM0' has been connected to the terminal 'D'.

'G' mapped to 'G'.

The net 'VSS' of instance 'MNM0' has been connected to the terminal 'G'.

'S' mapped to 'S'.

The net 'VDD' of instance 'MNM0' has been connected to the terminal 'S'.

'B' mapped to 'B'.

The net 'net49' of instance 'MNM0' has been connected to the terminal 'B'.

#####################################

MOS Instance: MNM4

#####################################

...Searching for a valid mapping in the dev-map file...

        ...Bingo! Cell mapped to N_11_SPRVT->symbol.

Now, searching for the cellview N_11_SPRVT->symbol in ref libs...

    ...in umc65sp: Bingo! Found the master cellview: N_11_SPRVT->symbol.

instName->'MNM4' is created.

propName->'subtype'; propVal->'NA' is created.

propName->'w'; propVal->'4E-05' is created.

propName->'l'; propVal->'1.2E-07' is created.

propName->'m'; propVal->'4' is created.

'D' mapped to 'D'.

The net 'VDD' of instance 'MNM4' has been connected to the terminal 'D'.

'G' mapped to 'G'.

The net 'net40' of instance 'MNM4' has been connected to the terminal 'G'.

'S' mapped to 'S'.

The net 'net49' of instance 'MNM4' has been connected to the terminal 'S'.

'B' mapped to 'B'.

The net 'VSS' of instance 'MNM4' has been connected to the terminal 'B'.

INFO (CDLIN-54): CDL In successfully created the schematic view IO_lib_SP_2_5V_Inline_Reg_VT.IDDBREAK::netlist. Read the log file 

'conn2sch_IDDBREAK.log' for more information.