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routing P/G for I/O cells

Hi everybody,

Can somebody help me, please, telling how to route P/G pins for I/O cells having a different voltage supply from the core power supply? Beside the I/O cells’ pins connected to the core and included in the verilog netlist I have few pins belonging to the I/O cell and their own power supply pins (vdde and gnde) that should be tied to a different power supply. What is the common way to do such connections?

Thank you a lot.

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Kari over 11 years ago

these are usually connected by abutment of the IO ring. you may need to add IO fill cells to close the gaps.
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Kari over 11 years ago

these are usually connected by abutment of the IO ring. you may need to add IO fill cells to close the gaps.
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