Stats

  • Locked Locked
  • Replies 2
  • Subscribers 93
  • Views 13744
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Is there a way to specify antenna info for top-level terminals?

FriendFX

Hi, I'm using Encounter to build a digital block. I have placed the top-level terminals using "editPin" commands and that works fine. After building the block and integrating it with the rest of the chip (and running it through Calibre), I get antenna violations for some of these terminals which feed into gates which are not "known" by Encounter because they're outside of the block built by Encounter.

I guess the easiest way to deal with that problem would be adding antenna information to the top-level terminals which feed into gates to make Encounter "jump" up to top metal just before connecting to the terminal. But I am not sure how or if that is possible at all to add/modify antenna information.

I looked into "dbSet", but all antenna information seems to be read-only and for the top-level terminals, there doesn't even seem to be any antenna information attached to them at all: "dbGet [dbGet -p1 top.terms.name {adc_out_o[9]}].antennas" returns 0x0.

Any ideas?

  • Comon practice is to use abstract generator (just  type "abstract" in terminal) between "building the block" and "integrating it with the rest of the chip". With caorrect setup it produce LEF with antenna data.

    Another way is extend your LEF with antenna data manualy for each pin. If your designis have no a lot of pins and should be integrated in cramped environmentyou can use not real but small enough values for each pin antena parameters.

     Hope it helps.

  • Hi there,

    I know that I'm responding to a very old topic but maybe this will help someone who has the same or a similar problem.

    Recently I had to fit a block from Encounter into a manually routed design in Virtuoso. However since Encounter didn't know about the antenna specifications at the blocks IO's, combining the layouts lead to numerous antenna rule violations. To solve the problem I extracted the antenna information (command abstract) for each interfacing pin of the Virtuoso layout and created a LEF file with "antenna marker" cells for each pin. The "antenna markers" are just tiny rectangles with a single pin connected to the block-pins net, placed next to the pin itself (before routing). After routing, the markers can be removed easily. Everything can be well automated with scripts.

    Of course I'm interested in better solutions.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.