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Make macro block pin visible in higher hierarchy

Mikutine

Hello all,

I have the following situation in SOC Encounter:

I have made a design X, which uses some standard cells, and some macro blocks. One type of macro block should have an input or output port. This should also be an input or output port of the design X, but should not be connected to the side of the design X. 

I want to utulise two of the design X, into a top-level design Y. For this I want to turn the design X into a macro block (LEF/LIB). In my top-level design Y I want to connect the two design X macros through the input/output ports i mentioned above.

(See attached pdf with explanation drawing) 

What is the best possible way to do this?

Whatever I try, after the 'saveModel' command which outputs the LEF and the LIB, these input/output ports I mentioned above are not visible, and neighter are the metal layers specified in the LEF file.

If someone knows the solution to this, please let me know. 

macro pin problem explained.pdf
Parents
  • Maybe I should be more specific. These mentioned macro blocks are supposed to be TSVs (through silicon via). This is not possible in encounter, so I try to model this is 2D. In reality no wire excists between the two pins. This is why I want a direct connection, so I can leave the wiring delay out in my calculations.
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  • Maybe I should be more specific. These mentioned macro blocks are supposed to be TSVs (through silicon via). This is not possible in encounter, so I try to model this is 2D. In reality no wire excists between the two pins. This is why I want a direct connection, so I can leave the wiring delay out in my calculations.
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