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DRC Fixing in Encounter

metalhead

 Hello

Ive been trying to do some DRC fixing in Cadence Ecounter. The basic problem I am facing is offgrid/nogrid routing errors. I tried setting the routeOngrid option true and routed the design again. But still there is no significant reduction in the number of errors. The total number of DRC errors is in the range of 1 million plus of which 900,000 odd are nogrid violations and 100,000 odd are offgrid. Can anyone please tell me about things I could do in routing by which I can fix these errors? Is routing/incremental routing the only way to fix DRC errors in Encounter? Any suggestions/replies are appreciated

Parents

  •  I just ran verifyTracks on an old 65nm block  .... STMicro good vendor!

    #Start checking floorplan tracks ...
    #Start checking preferred tracks integrity ...
    #Checking preferred tracks integrity done.
    #Start checking pin accessing against defined tracks ...
    # M1           H   Track-Pitch = 0.200    Line-2-Via Pitch = 0.190
    # M2           V   Track-Pitch = 0.200    Line-2-Via Pitch = 0.200
    # M3           H   Track-Pitch = 0.200    Line-2-Via Pitch = 0.200
    # M4           V   Track-Pitch = 0.200    Line-2-Via Pitch = 0.200
    # M5           H   Track-Pitch = 0.200    Line-2-Via Pitch = 0.200
    # M6           V   Track-Pitch = 0.800    Line-2-Via Pitch = 0.800
    # M7           H   Track-Pitch = 0.800    Line-2-Via Pitch = 0.800
    # AP           V   Track-Pitch = 5.000    Line-2-Via Pitch = 5.700
    #Build pin access layout completely
    #
    #Total number of pins = 6113965
    #       Total number of on-track standard cell pins (via accessing) = 6113965 (100.00 percent)
    #       Total number of off-track standard cell pins (via accessing) = 0
    #Total number of pins blocked by SNET = 0
    #Check tracks done and successfully.

    Notice the Track-Pitch's are all multiples and everything lines up nicely.

    Normally the routing grid is correctly defined by the "floorplan" sizing command, but just in case try the  "generateTracks" command to regenerate the routing grid and recheck with "verifyTracks".
    If that doesn't work you have some research to do.

    Start with the  <technology>.lef which defines the basic metal routing PITCH and standard cell SITE CORE size.
    The SITE CORE X dimension is usually the same as the vertical M2 PITCH so that M2 wires can directly via down to an M1 pin.
    Typically the vertical routing grid is offset  from the placement site array by half a pitch.

    LAYER M2
      TYPE ROUTING ;
      DIRECTION VERTICAL ;
      PITCH 0.2 ;

    SITE CORE
      CLASS CORE ;
      SYMMETRY X Y ;
      SIZE 0.2 BY 2.6 ;
    END CORE

    Debugging blind is very difficult, but if you look at at the previously mentioned guideline documentation you should get the overall picture.

    Shawn

Reply

  •  I just ran verifyTracks on an old 65nm block  .... STMicro good vendor!

    #Start checking floorplan tracks ...
    #Start checking preferred tracks integrity ...
    #Checking preferred tracks integrity done.
    #Start checking pin accessing against defined tracks ...
    # M1           H   Track-Pitch = 0.200    Line-2-Via Pitch = 0.190
    # M2           V   Track-Pitch = 0.200    Line-2-Via Pitch = 0.200
    # M3           H   Track-Pitch = 0.200    Line-2-Via Pitch = 0.200
    # M4           V   Track-Pitch = 0.200    Line-2-Via Pitch = 0.200
    # M5           H   Track-Pitch = 0.200    Line-2-Via Pitch = 0.200
    # M6           V   Track-Pitch = 0.800    Line-2-Via Pitch = 0.800
    # M7           H   Track-Pitch = 0.800    Line-2-Via Pitch = 0.800
    # AP           V   Track-Pitch = 5.000    Line-2-Via Pitch = 5.700
    #Build pin access layout completely
    #
    #Total number of pins = 6113965
    #       Total number of on-track standard cell pins (via accessing) = 6113965 (100.00 percent)
    #       Total number of off-track standard cell pins (via accessing) = 0
    #Total number of pins blocked by SNET = 0
    #Check tracks done and successfully.

    Notice the Track-Pitch's are all multiples and everything lines up nicely.

    Normally the routing grid is correctly defined by the "floorplan" sizing command, but just in case try the  "generateTracks" command to regenerate the routing grid and recheck with "verifyTracks".
    If that doesn't work you have some research to do.

    Start with the  <technology>.lef which defines the basic metal routing PITCH and standard cell SITE CORE size.
    The SITE CORE X dimension is usually the same as the vertical M2 PITCH so that M2 wires can directly via down to an M1 pin.
    Typically the vertical routing grid is offset  from the placement site array by half a pitch.

    LAYER M2
      TYPE ROUTING ;
      DIRECTION VERTICAL ;
      PITCH 0.2 ;

    SITE CORE
      CLASS CORE ;
      SYMMETRY X Y ;
      SIZE 0.2 BY 2.6 ;
    END CORE

    Debugging blind is very difficult, but if you look at at the previously mentioned guideline documentation you should get the overall picture.

    Shawn

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