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ETS Flow CCS versus NLDM models

maliv
Hello All,

We have been using NLDM models for a long time now.Our ETS Flow tuned with NLDM models, closely compares with third party sign-off tool and the timing difference most of the times is within 2%.

However, the same flow, does not compare well with CCS models. We are seeing 3-5% timing difference between ETS and third party tool.

Can someone suggest on how CCS/ECSM correlate with silicon results. Should we definitely consider moving to CCS, if yes why?

Let me know if you need more information.

Thanks and Regards,

Mali

  • Mali
    What technology node are currently in? 
    Which type of timing model is your third party sign-off tool using?


    If signoff is still using NLDM models, it may turn out to be that ETS + CCS or ECSM models are 3-5% more accurate.
    If both are using the same model types we normally expect better timing correlation, especially if both timing engines are using the same parasitic extraction source files.

    There is lots of online documentation worth reading ....

    Shawn
     

  • We are currently using 28hpm.

     I am comparing

     ETS + NLDM with TPT + NLDM (2% difference average for a bunch of our designs)

     ETS + CCS with TPT + CCS (3-5% difference)

     So, the comparison is based on same library models and same parasitic source files.

     So does anyone here have any data on how close CCS is with respect to silicon results. +/- any percent value on the average.

     Should we consider moving to CCS/ECSM for signoff, any strong reasons.

     Regards,

     Mali

  • Mali:

    I'm sure your local Cadence AppEng can tweak "out of the box" ETS+CCS to be more in line with PT+CCS.
    ETS + NLDM vs ETS + CCS  comparison results might be more informative.

    In the end working silicon is the ultimate goal!  ( and what your silicon vendor dictates for signoff )  
    We started to see the NLDM flow fall apart at 65nm, so much extra margin was built into the vendor flow to cover the modeling inaccuracies, that our data path performance suffered.
    It took a lot of pressure to convince the vendor to switch to the more accurate CCS based flow and remove the "excessive" margin,  that got our silicon back up to speed and reduced power to boot

    At 28nm I don't think we could easily achieve working silicon with NLDM models. I'm surprised that your silicon vendor even supports NLDM based signoff. ( then again fabs do love the excess margin )

    Start with the Cadence online documentation,  then try general online searches to get a few second opinions.
    Second talk to your local Cadence AppEng and get the low down on what is required, then try and bring your silicon vendor in line.
    The next year(s) of your life depend on understanding all of the ramifications, 28nm timing closure can be absolute hell or just rather warm . Using 3rd party signoff can also turn the thermostat way up.
     
    Shawn

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