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Steps to perform Place & Route from Synthesized Netlist

Hi,

I have a synthesezed netlist of my design (*.v file) and now I want to perform place & route as well inorder to determine more accurate timing results. I would like to know how P&R can be done with default constraints just to get a rough timing estimate. I have *.lib and *.lef library files for the technology. Do I also need a timing library for P&R?, I have googled a lot but I couldn't find a simple tutorial about it.

Thanks.

wally1 over 11 years ago

There is a tutorial for EDI System on Cadence Online Support:
http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=Training/Digital_IC_Design/EDI13.1_Tutorial.html
Hope this helps,
Brian
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