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Multi point CTS implementation

vamsi611

I have a netlist and def with single clock port clk.

I want to implement multi point cts with 4 clocks(clk1,clk2,clk3,clk4).They are equilent to clock port clk.

What are the flow steps in encounter to  implement this multipoint CTS.

(How can create 4 new clock ports and remove old clock port clk, how to take care of clock connectivity in the design and implementation of multi point CTS)

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  • Been there done that , but I would not do it the same way again.
    We used multiple  discrete  DLL drops points for a main clock in a physically large block.
    Basically we would run a regular placeDesign and then disconnect all of the clock leafs and reconnect them to the closest DLL with a tcl script.
    All fun and games until you get to timeDesign and realize you are now essentially randomly crossing clock domains.
    Even more fun when you add clock gating and  DFT scan reorder mode to the mix.

    Next time I would restrict the multiple clock domains to follow the logical hierarchy and the placement floorplan fences.
    i.e. moduleA has a placement fenceA and uses clkA , moduleB has a placement fenceB and uses clkB etc. etc.
    That way the manual clock edits to the verilog are simple you can predict / anticipate potential domain crossings timing issues.

    The KISS principle rules ( Keep It Simple Stupid ) especially where clock is concerned.

    First try a single central clock drop point, if your block is not too convoluted clockDesign with tuning can do a very good job.
    If you are trying to reduce total insertion delay,  manually route the top level clock tree root net to a central location in each of your hierarchical blocks.
    You will have to run some spice simulations to determine the optimal root routing style, start with, top two metals, double wide, quad via, double spaced.

    Shawn


     

Reply

  • Been there done that , but I would not do it the same way again.
    We used multiple  discrete  DLL drops points for a main clock in a physically large block.
    Basically we would run a regular placeDesign and then disconnect all of the clock leafs and reconnect them to the closest DLL with a tcl script.
    All fun and games until you get to timeDesign and realize you are now essentially randomly crossing clock domains.
    Even more fun when you add clock gating and  DFT scan reorder mode to the mix.

    Next time I would restrict the multiple clock domains to follow the logical hierarchy and the placement floorplan fences.
    i.e. moduleA has a placement fenceA and uses clkA , moduleB has a placement fenceB and uses clkB etc. etc.
    That way the manual clock edits to the verilog are simple you can predict / anticipate potential domain crossings timing issues.

    The KISS principle rules ( Keep It Simple Stupid ) especially where clock is concerned.

    First try a single central clock drop point, if your block is not too convoluted clockDesign with tuning can do a very good job.
    If you are trying to reduce total insertion delay,  manually route the top level clock tree root net to a central location in each of your hierarchical blocks.
    You will have to run some spice simulations to determine the optimal root routing style, start with, top two metals, double wide, quad via, double spaced.

    Shawn


     

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