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Multi point CTS implementation

vamsi611

I have a netlist and def with single clock port clk.

I want to implement multi point cts with 4 clocks(clk1,clk2,clk3,clk4).They are equilent to clock port clk.

What are the flow steps in encounter to  implement this multipoint CTS.

(How can create 4 new clock ports and remove old clock port clk, how to take care of clock connectivity in the design and implementation of multi point CTS)

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  • Vamsi ... you have almost got it!

    I still suggest starting with the simplest  clock possible and see if clockDesign can meet your requirements.
    Start with one drop, If not, try two, then three, then four........ no sense in making your life more complicated than it already is.  

    The only reason we required multiple clock drops was to reduce clock insertion latency on the high speed interface module to full custom ADC.
    The ADC was 16mm tall and the interface module was pitch matched at 2mm x 16mm,  we could not meet the maximum latency specification across the full 16mm distance.
    We ended up requiring  four clock drops, if I were to do this again I would request to have interface RTL coded into four separate self contained channels from the get go.
    The layout would then be one module replicated four times , too easy.

    Rant #1
    One thing the RTL designers don't seem to comprehend is the importance of logical hierarchy.
    An optimal logical hierarchy allows us to  decide  the optimal layout strategy in ... hmm ... layout.
    Layout can choose to use or ignore logical hierarchy ( partition, region, guide, modulePadding  etc etc etc )
    Flatland RTL coding offers the layout team no options but to take one possibly very difficult route.
    Sorry for the rant, I have to try and convince an RTL designers boss, that 1 man week re-coding / re-verifying will save me 4 weeks in layout.

    Shawn

Reply

  • Vamsi ... you have almost got it!

    I still suggest starting with the simplest  clock possible and see if clockDesign can meet your requirements.
    Start with one drop, If not, try two, then three, then four........ no sense in making your life more complicated than it already is.  

    The only reason we required multiple clock drops was to reduce clock insertion latency on the high speed interface module to full custom ADC.
    The ADC was 16mm tall and the interface module was pitch matched at 2mm x 16mm,  we could not meet the maximum latency specification across the full 16mm distance.
    We ended up requiring  four clock drops, if I were to do this again I would request to have interface RTL coded into four separate self contained channels from the get go.
    The layout would then be one module replicated four times , too easy.

    Rant #1
    One thing the RTL designers don't seem to comprehend is the importance of logical hierarchy.
    An optimal logical hierarchy allows us to  decide  the optimal layout strategy in ... hmm ... layout.
    Layout can choose to use or ignore logical hierarchy ( partition, region, guide, modulePadding  etc etc etc )
    Flatland RTL coding offers the layout team no options but to take one possibly very difficult route.
    Sorry for the rant, I have to try and convince an RTL designers boss, that 1 man week re-coding / re-verifying will save me 4 weeks in layout.

    Shawn

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