• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Digital Implementation
  3. LVS Issue with power

Stats

  • Locked Locked
  • Replies 0
  • Subscribers 91
  • Views 12657
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

LVS Issue with power

G Shyam
G Shyam over 11 years ago
I have got one issue in LVS 

In my design i have preplaced cell named PowerClamp 4 in number, each cell has different instance name, it has common pin name "VDDESD" "VSSESD" 
pin "VDDESD" connect to power net named VDD0P9 for two cells and other two cell connect to different power domain named VDD1P8

Now issue is, In layout they are seen as different power net due to different instance name but in source (spice file ) they look by cell type one pin has two power net and report as short.
layout is fine, we need to inform tool these are different nets in spice file, i understood the problem but couldn't reach the solution to resolve this.
  • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information