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Encounter cannot find a valid clock net / Timing library is not loaded

rexnyu
In SoC encounter 11.0, after I execute the following command:
 
createClockTreeSpec -output ../CTS/${DESIGN_NAME}_spec.cts \
   -bufferList BUFX2 BUFX4 INVX1 INVX2 INVX4 INVX8
 
 
It gives me the following message: 
 
CTS treats D-pins and I/O pins as non-synchronous pins by default.
If you want to change the behavior, you need to use the SetDPinAsSync
or SetIoPinAsSync statement in the clock tree specification file,
or use the setCTSMode -traceDPinAsLeaf {true|false} command,
or use the setCTSMode -traceIoPinAsLeaf {true|false} command
before specifyClockTree command.

*** End specifyClockTree (cpu=0:00:00.0, real=0:00:00.0, mem=345.0M) ***
<clockDesign CMD> ckSynthesis -report ../RPT/SboxWrapper/clock.report -forceReconvergent -breakLoop
Checking spec file integrity...
**WARN: (ENCCK-178):    CTS cannot find a valid clock net.
**WARN: (ENCCK-313):    You have not specified a clock tree. Use the specifyClockTree command to do so.
*** End ckSynthesis (cpu=0:00:00.0, real=0:00:00.0, mem=345.0M) ***
**clockDesign ... cpu = 0:00:00, real = 0:00:00, mem = 345.0M **
<CMD> optDesign -postCTS -hold -outDir ../RPT/SboxWrapper
**DIAG[opUtil.c:10662:update]: Assert "powerView != tocDefaultView"
**DIAG[opUtil.c:10667:update]: Assert "powerViewTlc"
**DIAG[opUtil.c:10662:update]: Assert "powerView != tocDefaultView"
**DIAG[opUtil.c:10667:update]: Assert "powerViewTlc"
**optDesign ... cpu = 0:00:00, real = 0:00:00, mem = 345.2M, totSessionCpu=0:00:05 **
**ERROR: (ENCOPT-6029): Timing Library is not loaded yet**ERROR: (ENCSYT-6692): [SoC_Encounter.tcl]: Invalid return code while executing "SoC_Encounter.tcl"
 
 
What could be the reason for this? My design does have a clock. 
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