Encounter Library Characterizer gate recognition fails

 Dear all,

I'm having a problem with the Encounter Library Characterizer tool in the ETS Suite.
I'm trying to characterize standard cells, however, I'm having a problem that keeps returning at a lot of forums, but never seems to get solved.

In the first step of characterization, the tool should detect the logic functions of my circuit. I'm using a simple inverter:

simulator lang = spectre
global vdd
global gnd
subckt inv A Y vdd gnd
    \+1 (Y A vdd vdd) ami06P w=6e-06 l=6e-07 as=9e-12 ad=9e-12 ps=9e-06 \
        pd=9e-06 m=1 region=sat
    \+0 (Y A gnd gnd) ami06N w=3e-06 l=6e-07 as=4.5e-12 ad=4.5e-12 ps=6e-06 \
        pd=6e-06 m=1 region=sat
ends inv

 I'm using this library (www.ece.umd.edu/.../ami06.lib) as a simple example to mess around with.The setup-file is this:

 // Encounter Library Characterizer setup file
Process typical{
    voltage = 5.0;
    temp = 25;
    Corner = "TT";
    Vtn = 0.67;
    Vtp = 0.92;
};

Signal std_cell {
    unit = REL;
    Vh=1.0 1.0;
    Vl=0.0 0.0;
    Vth=0.5 0.5;
    Vsh=0.8 0.8;
    Vsl=0.2 0.2;
    tsmax=2.0n;
};
   
Simulation std_cell{
    transient = 0.1n 80n 10p;
    dc = 0.1 4.5 0.1;
    bisec = 6.0n 6.0n 100p;
    resistance = 10MEG;
};

Index DEFAULT_INDEX{
    Slew = 0.100n 0.30n 0.7n 1.0n 2.0n;
    Load = 0.025p 0.05p 0.1p 0.3p 0.6p;
};

Margin m0 {
    setup     = 1.0 0.0 ;
    hold     = 1.0 0.0 ;
    release = 1.0 0.0 ;
    removal = 1.0 0.0 ;
    recovery = 1.0 0.0 ;
    width    = 1.0 0.0 ;
    delay     = 1.0 0.0 ;
    power     = 1.0 0.0 ;
    cap     = 1.0 0.0 ;
} ;

Nominal n0 {
    delay = 0.5 0.5 ;
    power = 0.5 0.5 ;
    cap   = 0.5 0.5 ;
} ;

set process(typical){
    simulation = std_cell;
    signal = std_cell;
    margin = m0;
    nominal = n0;
    index = DEFAULT_INDEX;
};

 The elccfg file in the running directory is this one:

# Setup stuff
SETUP = "setup.ss"
PROCESS = "typical"
SUBCKT = "dut.scs"
MODEL = "ami06.scs"

When I run this file in ELC:

db_open foo
set_var EC_SPICE_SIMPLIFY true
set_var EC_HALF_WIDTH_HOLD_FLAG true
set_var EC_SIM_NAME "spectre"
set_var EC_SIM_TYPE "spectre"
set_var EC_SPICE_SUPPLY1_NAMES "vdd"
set_var EC_SPICE_SUPPLY0_NAMES "gnd"
db_prepare -force
db_gate
db_close
exit

ELC does not recognize the simple inverter circuit. The resulting gate recognition is the following:

==============================
      DESIGN : INV
==============================
DESIGN ( INV );
//    =================
//     PORT DEFINITION
//    =================
    SUPPLY0 GND ( GND );
    SUPPLY1 VDD ( VDD );
    FEEDTHRU A ( A );
    FEEDTHRU Y ( Y );
//    ===========
//     INSTANCES
//    ===========
END_OF_DESIGN;

- feed-through ( A ) is found
- feed-through ( Y ) is found
 

As you can see, the A, Y ports are recognized as feedthrough, while they should be input and output ports. I've searched and read a lot about this problem, and it seems that this not so easy to solve. Especially since the variables to play with are very limited: I guess the problem can only be in the technology model, netlist, setup-file or cmd-file? I've tried (in my opinion) every reasonable alternative, and I do not seem capable to finish the flow correctly. 

Does anyone have any suggestions I can follow to overcome this problem? I know it is possible to edit/write the gate-file by hand, but since I'm planning on doing a lot of characterization, this is not really an option. Also, I would like to pass the entire flow automatically for convenience.

Any suggestions are welcome,

 Kind regards,

Hans