Timing constraine problem in synthesis

i had design a divider and a up/down counter for a section of my project.Input frequency of clock is 50mhz and it is divided by 50(1mhzclock) to clock up/down counter.but after synthesis their exist a timing problem to registers define for up/down counter

timing problem is

THE FOLLOWING SEQUENTIAL CLOCK PIN HAVE NO CLOCK WAVEFORM DRIVING THEM.NO TIMING CONSTRAINE WILL BE DERIVED FOR PATH LEADING TO AND FROM THESE PINS(which is registers define in up/down counter)

so how can i define clock(1mhz) to up/down counter(which is divided from input clock of 50mhz)?