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Can someone help me figure out where does power analysis of Cadence Encounter RTL Compiler comes from

Haoxiang

Hi all,

 New to this area, I have two questions that need your help. 

1st, when I get the power analysis from Cadence Encounter RTL Compiler, It automatically shows Leakage, Internal, Net and Switching Power of the generated schematic. But then I get comfused, under which input pattern does the Compiler infer all the power values, especially switching power, since it's directly related to the frequency of input?

 2nd, what's the difference between Leakage Power and Internal Power? And does Net Power means power consumed from the interconnect? I get confusion about these terms

 Thank you very much for your notice and help!

Best 

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  • ajay01

     1.Generaly basic power information come from .lib .like how much leakage when cell have different-different logic.for each cell in stander cell lib. and other information come from collapsed/port view of standered cell and macro.

    2.Two type of power in CMOS :

    a.dynamic power(switching power)

    b.static power(internal power)

    And leakage power is leakge of both dynamic and static IR drop.

     For detail of CMOS power:

    http://en.wikipedia.org/wiki/CMOS#Power:_switching_and_leakage

    Thanks,

    Ajay

Reply
  • ajay01

     1.Generaly basic power information come from .lib .like how much leakage when cell have different-different logic.for each cell in stander cell lib. and other information come from collapsed/port view of standered cell and macro.

    2.Two type of power in CMOS :

    a.dynamic power(switching power)

    b.static power(internal power)

    And leakage power is leakge of both dynamic and static IR drop.

     For detail of CMOS power:

    http://en.wikipedia.org/wiki/CMOS#Power:_switching_and_leakage

    Thanks,

    Ajay

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