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Can someone help me figure out where does power analysis of Cadence Encounter RTL Compiler comes from

Haoxiang

Hi all,

 New to this area, I have two questions that need your help. 

1st, when I get the power analysis from Cadence Encounter RTL Compiler, It automatically shows Leakage, Internal, Net and Switching Power of the generated schematic. But then I get comfused, under which input pattern does the Compiler infer all the power values, especially switching power, since it's directly related to the frequency of input?

 2nd, what's the difference between Leakage Power and Internal Power? And does Net Power means power consumed from the interconnect? I get confusion about these terms

 Thank you very much for your notice and help!

Best 

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  • ajay01

    Hi Chaitanya,

    You were facing short violation but you have not mention number of short violation :

    1.if its more then 50 then you need to check with design routablity.

    Its due to congestion then you need to take care it from floorplan.

    2.if its less then 20 ou can do manual fixing.

    If you are not good in manual fixing then you can try below step:

    Delete all net which having short by using below command:

    editDelete -net {net name}

    Then re-route those net by routeDesign -selected

    Thanks,

    Ajay

Reply
  • ajay01

    Hi Chaitanya,

    You were facing short violation but you have not mention number of short violation :

    1.if its more then 50 then you need to check with design routablity.

    Its due to congestion then you need to take care it from floorplan.

    2.if its less then 20 ou can do manual fixing.

    If you are not good in manual fixing then you can try below step:

    Delete all net which having short by using below command:

    editDelete -net {net name}

    Then re-route those net by routeDesign -selected

    Thanks,

    Ajay

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