No driven nets

 Dear all,

I am facing an issue with Encounter which i do not understand.

In my digital block I forward my clock input to another clock output pin on my digital block.

VHDL :  CLK_OUT <= CLK_IN;

The reason why I am doing this is that my digital block creates some outputs (I will name them DIG_OUT here..) which are clocked with the CLK_IN clock port,

These outputs with the forwarded CLK_OUT clock are fed to another separate block somewhere else on chip in the same mixed signal die.

In order to constrain my DIG_OUT ports with respect to the CLK_OUT port i used the following contraints:

First I constrained my CLK_OUT :

create_generated_clock -name clk_output_clock -source [get_ports CLK_IN] -multiply_by 1 [get_ports CLK_OUT]

Then I constrained my output port DIG_OUT:

set output_delay -clock [get_clocks {clk_output_clock}] -max [expr $tSU] [get_ports {DIG_OUT[*]}]

set output_delay -clock [get_clocks {clk_output_clock}] -min [expr -$tH] [get_ports {DIG_OUT[*]}]

, where $tSU and $tH represents the worst case setup and hold time of the receiving flipflops in the other digital design further away on the die. Trace length between data and clock lines from DIG_OUT and CLK_OUT to the destination digital block on the die are equal.

After clock tree synthesis, and mapping to the final layout of my final design I can see that encounter has included one clock buffer between the CLK_OUT and CLK_IN port together with some connecting traces. I can see these element in my layout so that is good.

 However, Encounter reports show one report which I really do not understand, a no-drivenNets report:

No-driven Nets Information Page

 * TODO:

assign_net_CLK_OUT_0
assign_net_CLK_OUT_1
CLK_IN__Exclude_0_NET

The corresponding mapped layout verilog shows a connection from CLK_IN to an clk buffer and the output of the clk buffer to the CLK_OUT pin.

Generated verilog gives this:

   cnbfx2 CLK_IN__Exclude_0 (.Z(CLK_OUT),
    .A(CLK_IN));
 

However, it seems as if the connecting traces in the layout are not connected in the corresponding verilog (although they are clearly visible and connected in the layout..). 

Can anybody explain me what is happening here and why this only occurs with this buffererd output clock signal?

With kind regards,

Henk