Clock multiplexer SDC

 Hi,

Could anyone please help me how to write SDC constraint file for clock generation as in the file?
I'd like to generate two clocks, one for processor core, the other one for peripherals. Core and peripheral clock can be multiplexed independantly. The code for multiplexer and clock divider is below.

module clock_multiplexer(
    input wire  [3:0]   clk_input,
    input wire          rst,
    input wire  [3:0]   sel,
    output wire clk_output
);

wire    [3:0]   clk_and;
wire    [7:0]   dff_out;

assign  clk_and[0] = clk_input[0] & dff_out[1];
assign  clk_and[1] = clk_input[1] & dff_out[3];
assign  clk_and[2] = clk_input[2] & dff_out[5];
assign  clk_and[3] = clk_input[3] & dff_out[7];

assign  clk_output  =   clk_and[0] | clk_and[1] | clk_and[2] | clk_and[3];

dffnr0      #(.N(1))    clk0_dff0(.clk(clk_input[0]),.rst(rst), .Q(dff_out[0]), .D(sel[0]&~dff_out[3]&~dff_out[5]&~dff_out[7]));
dffnr0neg   #(.N(1))    clk0_dff1(.clk(clk_input[0]),.rst(rst), .Q(dff_out[1]), .D(dff_out[0]));

dffnr0      #(.N(1))    clk1_dff0(.clk(clk_input[1]),.rst(rst), .Q(dff_out[2]), .D(sel[1]&~dff_out[1]&~dff_out[5]&~dff_out[7]));
dffnr0neg   #(.N(1))    clk1_dff1(.clk(clk_input[1]),.rst(rst), .Q(dff_out[3]), .D(dff_out[2]));

dffnr0      #(.N(1))    clk2_dff0(.clk(clk_input[2]),.rst(rst), .Q(dff_out[4]), .D(sel[2]&~dff_out[1]&~dff_out[3]&~dff_out[7]));
dffnr0neg   #(.N(1))    clk2_dff1(.clk(clk_input[2]),.rst(rst), .Q(dff_out[5]), .D(dff_out[4]));

dffnr0      #(.N(1))    clk3_dff0(.clk(clk_input[3]),.rst(rst), .Q(dff_out[6]), .D(sel[3]&~dff_out[1]&~dff_out[3]&~dff_out[5]));
dffnr0neg   #(.N(1))    clk3_dff1(.clk(clk_input[3]),.rst(rst), .Q(dff_out[7]), .D(dff_out[6]));

endmodule

module clock_divider(
    input wire clk,
    input wire rst,
    output wire clk_out
);

parameter DIV_RATE = 3;

reg [DIV_RATE-1:0]  count;

assign  clk_out = count[DIV_RATE-1];

always @ (posedge clk or negedge rst)
begin
    if (~rst) begin
        count <= 0;
    end else begin
        count <= count + 1;
    end
end

endmodule

module clock_divider_gen(
    input wire          clk,
    input wire          rst,
    output wire [3:0]   clk_out
);

reg [2:0]  count;

assign  clk_out = {count,clk};

always @ (posedge clk or negedge rst)
begin
    if (~rst) begin
        count <= 0;
    end else begin
        count <= count + 1;
    end
end

endmodule