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non-clock tree cells on clock tree paths

chris06

Hello,

 

I have a question regarding the use of non-clock tree cells on clock tree paths.

The netlist post-synthesis that I have, contains standard muxes and gating-elements on clock paths.

During the P&R clock-tree-synthesis step, clock tree buffers are inserted but the standard muxes and gating elements are not swapped to their "clock cell" version. 

I have 2 questions:

1/ Is there a way to force "RTL compiler"  tool to use only clock cells on clock tree paths when synthesizing the netlist?

2/ Is there a way to force "Encounter" tool to swap the non-clock-cells on clock paths to their "clock cell" version during clock tree synthesis step?  I mean is there a way to fully resynthesize the clock paths with clock tree cells?

 

Thanks in advance for your help.

Best Regards

Chris 

 

 

  •  Automatically ? Not that I am aware of...........
    1) RTL compiler - You manually instantiate specific clock tree cells rather than infer a mux.
    2) ENCOUNTER - You manually ecoChangeCell to the specific clock tree cell.

    Shawn

  • Thanks Shawn for your feedback.

    Actually I use the methodology you described in 2/. I list all the cells of the different clock-trees and then swap them automatically to their "clock-cell" version. The problem I'm facing is that lot of the cells used in these clock-trees don't have an equivalent "clock-cell". For example a MUX4:1 doesn't have a CLKMUX4:1 equivalent but only CLKMUX2:1. Which means that I have to do much tricky things than simply using ecoChangeCell. Anyway, if there is no easier way I'll have to do it manually.

     

    Thanks again and best regards,

    Chris  

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