Clock Tree Synthesis of a delay chain (tapped delay line)

In RTL, clock buffers and MUXes are used to create a delay chain/tapped delay line. These are preserved in synthesis and hence they appear in the netlist.

If this netlist is used, during Clock Tree Synthesis (CTS) stage, the tool (SoC Encounter) hangs and does not move forward saying that the clocks are already built and cannot be removed. If delete clock tree option is removed and CTS is run again, it comes out with a message that the clock has already been built and will not move forward.

I tried making the input of the delay chain as a leaf pin, which enables me to route the initial part of the clock. However, since I defined it as a leaf pin, it does not trace it further and the output of the delay chain is not built as a clock tree.

Any idea as to how to proceed with CTS for this? Do I need to specify anything specifically in the ctstch file?