Stats

  • Locked Locked
  • Replies 0
  • Subscribers 91
  • Views 12810
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

sub threshold leakage power analysis and optimization

amuidhay

Hi,

Im very new to cadence. Is it possible to analyse leakage power in low digital circuits at circuit level? what is the difference between leakage power analysis at circuit level and at logic level? which tool is used to do so? I dont know how to..where to start with? My aim is to take tablet PC as a reference..and minimize sub threshold leakage power particularly in digital circuits of tablet PC architecture... results in reduction of its static power dissipation.

It would be very useful if i get any quick response. Thanks. 

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.