ELC cannot run db_spice

 hello.

I use ELC to character INV and NAND2,when I type db_spice ,it shows 

   DESIGN        PROCESS       #ID         STATUS     IPDB
-------------+-------------+----------+--------------+-----------
INVX1          typical       D0000         SIMULATE    foo        
INVX1          typical       D0001         SIMULATE    foo        
============|=============|=============|==========|==============
INVX1          typical       2          2            foo        
NAND2X1        typical       D0000         SIMULATE    foo        
NAND2X1        typical       D0001         SIMULATE    foo        
NAND2X1        typical       D0002         SIMULATE    foo        
NAND2X1        typical       D0003         SIMULATE    foo        
NAND2X1        typical       D0004         SIMULATE    foo        
NAND2X1        typical       D0005         SIMULATE    foo        
NAND2X1        typical       D0006         SIMULATE    foo        
NAND2X1        typical       D0007         SIMULATE    foo        
============|=============|=============|==========|==============
NAND2X1        typical       8          8            foo        
--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*
 2014-07-23 16:21:58 (2014-07-23 08:21:58 GMT) : Vectors Launched 10/10
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
               Simulation Summary               
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
-------------+-------------+----------+--------------+-----------
-------------+-------------+----------+------------+-----------+------------
   DESIGN    |   PROCESS   |   #ID    |   STAGE    |  STATUS   |    IPDB
-------------+-------------+----------+------------+-----------+------------
INVX1          typical       D0000     SIMULATE     FAIL        foo        
INVX1          typical       D0001     SIMULATE     FAIL        foo        
NAND2X1        typical       D0000     SIMULATE     FAIL        foo        
NAND2X1        typical       D0001     VERIFICATE   PASS        foo        
NAND2X1        typical       D0002     SIMULATE     FAIL        foo        
NAND2X1        typical       D0003     VERIFICATE   PASS        foo        
NAND2X1        typical       D0004     SIMULATE     FAIL        foo        
NAND2X1        typical       D0005     VERIFICATE   PASS        foo        
NAND2X1        typical       D0006     SIMULATE     FAIL        foo        
NAND2X1        typical       D0007     VERIFICATE   PASS        foo        
-------------+-------------+----------+------------+----------

[INFO(db_spice)] Check the encounterlc.log/<ipdb_name>/<DESIGN>_<PROCESS>_<ID>.log file to determine the cause of the failure. The SPICE simulation log file can be found in the /home/IC_design/VLSI/ELC/encounterlc.work/<DESIGN>_<PROCESS>_<ID>/ directory.

-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
 - Total Simulation : 10
 - Total Passed     : 4(40.00%)
 - Total Failed     : 6(60.00%)
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-

and My dut,scs is

simulator lang=spectre

subckt NAND2X1 in1 in2 out vdd gnd
    \+3 (vdd in2 out vdd) tsmc25P w=4.5e-06 l=3e-07 as=2.025e-12 \
        ad=3.375e-12 ps=9e-07 pd=6e-06 m=1 region=sat
    \+2 (out in1 vdd vdd) tsmc25P w=4.5e-06 l=3e-07 as=3.375e-12 \
        ad=2.025e-12 ps=6e-06 pd=9e-07 m=1 region=sat
    \+1 (out in2 _6 gnd) tsmc25N w=2.7e-06 l=3e-07 as=1.215e-12 ad=2.025e-12 \
        ps=9e-07 pd=4.2e-06 m=1 region=sat
    \+0 (_6 in1 gnd gnd) tsmc25N w=2.7e-06 l=3e-07 as=2.025e-12 ad=1.215e-12 \
        ps=4.2e-06 pd=9e-07 m=1 region=sat
ends NAND2X1

subckt INVX1 in out vdd gnd
    \+1 (out in vdd vdd) tsmc25P w=4.5e-06 l=3e-07 as=3.375e-12 \
        ad=3.375e-12 ps=6e-06 pd=6e-06 m=1 region=sat
    \+0 (out in gnd gnd) tsmc25N w=2.7e-06 l=3e-07 as=2.025e-12 ad=2.025e-12 \
        ps=4.2e-06 pd=4.2e-06 m=1 region=sat
ends INVX1
~       

my setup.ss is ~

Process typical {
        Voltage = 2.5;
        temp = 25;
        Corner = "TT";
        Vtn = 0.67;
        Vtp = 0.92;
};

Process best {
        voltage = 5.5;
        temp = 0;
        Corner = "FF";
        Vtn = 0.63;
        Vtp = 0.89;
};
Process worst {
        voltage = 4.5;
        temp = 125;
        Corner = "SS";
        Vtn = 0.71;
        Vtp = 0.92;
};
Signal  std_cell {
        unit = REL;
        Vh = 1.0 1.0;
        Vl = 0.0 0.0;
        Vth = 0.8 0.8;
        Vsh = 0.8 0.8 ;
        Vsl = 0.2 0.2;
        tsmax = 2.0n;
};
Signal  std_cell_6710 {
        unit = REL ;
        Vh = 1.0 1.0 ;
        Vl = 0.0 0.0 ;
        Vth = 0.3 0.7 0.3 0.7;
        Vsh = 0.8 0.8 ;
        Vsl = 0.2 0.2 ;
        tsmax = 2.0n;
};
Signal VDD5.0V  {
       unit = ABS ;
       Vh = 5.0 5.0 ;
       Vl = 0.0 0.0 ;
       Vth = 2.5 2.5 ;
       Vsh =  2.0 2.0 ;
       Vsl = 0.5 0.5 ;                         tsmax = 2.0n;
};

Signal VDD2.5 {

       unit = ABS ;
       Vh  = 2.5 2.5 ;
       Vl = 0.0 0.0 ;
       Vth = 1.25 1.25 ;
       Vsh = 2.0 2.0 ;
       Vsl = 0.5 0.5 ;
       tsmax = 2.0n ;
 };
Simulation std_cell {
           transient = 0.1n 80n 10p ;
           dc = 0.1 4.5 0.1 ;
           bisec = 6.0n 6.0n 100p ;
//           resistance = 10K ;
           resistance = 10MEG;
};
Index DEFAULT_INDEX {
      Slew = 0.1n 0.3n 0.7n 1.0n 2.0n ;
      Load = 0.025p 0.05p 0.1p 0.3p 0.6p;
};
Index X1 {
      Slew = 0.1n 0.3n 0.7n 1.0n 2.0n ;
      Load = 0.025p 0.05p 0.1p 0.3p 0.6p;
};
Index X4 {
      Slew = 0.1n 0.3n 0.7n 1.0n 2.0n ;
      Load = 0.1p 0.2p 0.4p 1.2p 2.4p;
};
Index IO5*5 {
      Slew = 0.1n 0.3n 0.6n 1.3n 3.0n ;
//      Load = 5p 10p 20p 50p 75p;
       Load = 0.05p 0.10p 0.20p 0.50p 0.75p;
};
Group POWR {
      PIN = *.Vdd *.Vdd2;
};
Group Core_Pins {
      PIn = *.DO *.DI ;
};
Group Pad_Pins {
      PIN = *.YPAD;
};
Group Clk_Slew {
       PIN = *.CLK ;
};

Group X1 {
      CELL = 8X1;
};
Margin m0 {
       setup = 1.0 1.0 ;
       hold = 1.0 1.0 ;
       release = 1.0 1.0 ;
       removal = 1.0 0.0 ;
       recovery = 1.0 1.0 ;
       width = 1.0 1.0 ;
       delay = 1.0 1.0 ;
       power = 1.0 0.0 ;
       cap = 1.0 0.0 ;
};
Norminal n0 {
         delay = 0.5 0.5 ;
         power = 0.5 0.5 ;
         cap = 0.5 0.5 ;
};
set process (typical ,best , worst ) {
         simulation =std_cell ;
         signal = std_cell_6710;
         margin = m0;
         norminal = n0;
};
set index (typical ,best , worst ) {
          Group(X1) = X1;
          Group(X4) = X4;
          Group(Pad_Pins) = IO5*5;
          Group(Core_Pins) = X4;
          Group (Clk_Slew) = Clk_Slew ;
};
set signal (typical ,best ,worst ) {
           Group(POWR) = VDD2.5V ;
};
 

can anyone help me solve this , >_<,   thanks

Liu