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Pads on 3D IC

Hello,

I am a little confused about an issue. At the design of a 3D ic is it possible to have I/O pads at all the different layers? I have see many algorithms (i.e. for partition, placement) claiming that you can have I/O pads at every layer. In the other hand, i have heard that by manufacruring aspect you can have I/O pads only to one layer. Which scenario is the most reliable? Also, if you can give me a refference it would help too.

thanks.

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