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Cannot find output terms for clock synthesis

FMRLI

Hi,

I am getting an error while doing clock tree synthesis in encounter 10.1. It showing that
**ERROR: (ENCCK-158): Cannot find output terms for clock clk_in/ANAIO.

Here pad inastant name is "clk_in" and pin name is "ANAIO".

Clock tree specification file is

        AutoCTSRootPin clk_in/ANAIO

        NoGating rising               # (for auto CTS on a net)
        Buffer HS65_LS_BFX2 HS65_LS_BFX4 HS65_LS_BFX7 HS65_LS_IVX2 // name of buffer used for CTS
       
       MaxDelay 5ns
       MinDelay 0ns
       MaxSkew 50ps
       End

 

 

 

 

 

  • Is the IO pad defined in the timing library?

    Brian

  • Thanks for reply, 

    Here I just written the .lef text for ANAIO pin, which is a core side pin for the clock signal. CTS runs on the pin-ANAIO direction is "OUTPUT". However, the actual pin direction is "INOUT" from the technology .lef.

    PIN ANAIO
       DIRECTION INOUT ;
       PORT
       CLASS CORE ;
       LAYER M2 ;
        RECT 6.400 110.350 23.200 112.000 ;
      END
      PORT
       LAYER M2 ;
        RECT 6.400 110.350 23.200 112.000 ;
       LAYER AP ;
        RECT 3.000 109.000 37.000 112.000 ;
      END

     

     

  • I tested this and verified the clock root cannot be an inout pin. I recommend temporarily setting the LEF pin direction to OUTPUT during CTS to workaround this.

    Brian

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