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Using Verilog Configurations with RTL Compiler

tfrechette

Created a verilog configuration to control the implementation of a module in a design.

config.v:

config lx6_config;
  design lx6_top;
  default liblist lx6lib;
endconfig

config lx4_config;
  design lx4_top;
  default liblist lx4lib;
endconfig

config my_config;
   design multi_core_tb;
   default liblist lx6lib lx4lib;
   instance multi_core_tb.lx6_inst  use lx6_config:config;
   instance multi_core_tb.lx4_inst  use lx4_config:config;
endconfig

This works in simulation. How would you implement this using RC?

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