Encounter Library Characterizer: db_output

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CELL PM_INV_X1_VDD:

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  now converting

[WARNING(alf2lib)] There is no ECSM-TIMING table for this cell in ALF.

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-> The spice netlist was extracted from Virtuoso using Calibre. 

-> This is my script file:

set_var EC_SIM_USE_LSF 1 

set_var EC_SIM_LSF_CMD " " 
set_var EC_SIM_LSF_PARALLEL 10

set_var EC_SIM_TYPE "hspice" 
set_var EC_SIM_NAME "hspice" 
set_var EC_SPICE_SIMPLIFY 1 
set_var EC_DISABLE_BUNDLING 1 
set_var EC_SPICE_SUPPY1_NAMES "VDD"
set_var EC_SPICE_SUPPY0_NAMES "VSS"

db_open basic_char
db_prepare -force
db_spice -s hspice -keep_log

db_output -process typical -alf carac.alf -lib carac.lib -report carac.report -state

alf2html -alf carac.alf -dir ./html

db_output -process typical -lib lib_ng.lib -state

db_close
exit

->This is my elccfg file:

SETUP = "/home/gme/gbmoura/astran/virtuoso/ELC_Nangate/setup_circuitosng.txt"

PROCESS = "typical"
SUBCKT = "/home/gme/gbmoura/astran/virtuoso/ELC_Nangate/circuitosng_VTG.sp"
MODEL = "/home/gme/gbmoura/astran/virtuoso/ELC_Nangate/Modelo_VTG.sp"

->This is my setup file:

//Setup file for simulation in 45nm

Process typical {
voltage = 1.1;
temp = 25;
Corner = "TT";
Vtn = 0.15;
Vtp = 0.15;
};

Process best{
voltage = 1.25;
temp = 0;
Corner = "FF";
Vtn = 0.15;
Vtp = 0.15;
};

Process worst{
voltage = 0.95;
temp = 125;
Corner = "SS";
Vtn = 0.15;
Vtp = 0.15;
};

Signal std_cell {
unit = REL ; // relative value
Vh = 1.0 1.0 ; // 100% rise/fall
Vl = 0.0 0.0 ; 
Vth = 0.5 0.5 ; // 50% rise/fall
Vsh = 0.8 0.8 ;
Vsl = 0.2 0.2 ;
tsmax = 2.0n ; // maximum output slew rate
};

Simulation std_cell {
transient = 0.2n 80n 10p ;
bisec = 4.0n 4.0n 10ps ; // binary search
resistance = 10K;
};

Index INV_X1 {
Slew = 0.00117378n 0.00472397n 0.0171859n 0.0409838n 0.0780596n 0.130081n 0.198535n ;
Load = 0.365616f 1.897810f 3.795620f 7.591250f 15.182500f 30.365000f 60.730000f ;
} ;

Index INV_X2 {
Slew = 0.00117378n 0.00472397n 0.0171859n 0.0409838n 0.0780596n 0.130081n 0.198535n ;
Load = 0.365616f 3.795620f 7.591250f 15.182500f 30.365000f 60.730000f 121.460000f ;
} ;

Index INV_X4 {
Slew = 0.00117378n 0.00472397n 0.0171859n 0.0409838n 0.0780596n 0.130081n 0.198535n ;
Load = 0.365616f 7.591250f 15.182500f 30.365000f 60.730000f 121.460000f 242.920000f ;
} ;

Index INV_X8 {
Slew = 0.00117378n 0.00472397n 0.0171859n 0.0409838n 0.0780596n 0.130081n 0.198535n ;
Load = 0.365616f 15.163400f 30.326800f 60.653600f 121.307000f 242.614000f 485.229000f ;
} ;

Index NAND2_X1 {
Slew = 0.00117378n 0.00472397n 0.0171859n 0.0409838n 0.0780596n 0.130081n 0.198535n ;
Load = 0.365616f 1.854900f 3.709790f 7.419590f 14.839200f 29.678300f 59.356700f ;
} ;

Index NAND2_X2 {
Slew = 0.00117378n 0.00472397n 0.0171859n 0.0409838n 0.0780596n 0.130081n 0.198535n ;
Load = 0.365616f 3.709780f 7.419560f 14.839100f 29.678200f 59.356500f 118.713000f ;
} ;

Index NAND2_X4 {
Slew = 0.00117378n 0.00472397n 0.0171859n 0.0409838n 0.0780596n 0.130081n 0.198535n ;
Load = 0.365616f 7.419590f 14.839200f 29.678400f 59.356800f 118.714000f 237.427000f ;
} ;

Index NOR2_X1 {
Slew = 0.00117378n 0.00472397n 0.0171859n 0.0409838n 0.0780596n 0.130081n 0.198535n ;
Load = 0.365616f 0.834466f 1.668930f 3.337860f 6.675730f 13.351500f 26.702900f ;
} ;

Index NOR2_X2 {
Slew = 0.00117378n 0.00472397n 0.0171859n 0.0409838n 0.0780596n 0.130081n 0.198535n ;
Load = 0.365616f 1.668930f 3.337860f 6.675730f 13.351500f 26.702900f 53.405800f ;
} ;

Index NOR2_X4 {
Slew = 0.00117378n 0.00472397n 0.0171859n 0.0409838n 0.0780596n 0.130081n 0.198535n ;
Load = 0.365616f 3.337840f 6.675690f 13.351400f 26.702700f 53.405500f 106.811000f ;
} ;

Group INV_X1{
CELL = *INV_X1 ;
} ;

Group INV_X2{
CELL = *INV_X2 ;
} ;

Group INV_X4{
CELL = *INV_X4 ;
} ;

Group INV_X8{
CELL = *INV_X8 ;
} ;

Group NAND2_X1{
CELL = *NAND2_X1 ;
} ;

Group NAND2_X2{
CELL = *NAND2_X2 ;
} ;

Group NAND2_X4{
CELL = *NAND2_X4 ;
} ;

Group NOR2_X1{
CELL = *NOR2_X1 ;
} ;

Group NOR2_X2{
CELL = *NOR2_X2 ;
} ;

Group NOR2_X4{
CELL = *NOR2_X4 ;
} ;

Margin m0 {
setup = 1.0 0.0 ;
hold = 1.0 0.0 ;
release = 1.0 0.0 ;
removal = 1.0 0.0 ;
recovery = 1.0 0.0 ;
width = 1.0 0.0 ;
delay = 1.0 0.0 ; 
power = 1.0 0.0 ; 
cap = 1.0 0.0 ;
} ;

Nominal n0 {
cap = 0.0:0.5:1.0 0.0:0.5:1.0 ; // rise / fall
check = 1.0:1.0:1.0 1.0:1.0:1.0 ; // rise / fall
current = 0.0:0.5:1.0 0.0:0.5:1.0 ; // rise / fall
power = 0.0:0.5:1.0 0.0:0.5:1.0 ; // rise / fall
slew = 0.0:0.5:1.0 0.0:0.5:1.0 ; // rise / fall
delay = 0.0:0.5:1.0 0.0:0.5:1.0 0.0:0.5:1.0; // rise / fall / Z
delay = 0.5 0.5 ; // as rise fall
power = 0.5 0.5 ; 
cap = 0.5 0.5 ;
} ;

set process (best,typical,worst) {
simulation = std_cell ;
index = X1 ;
signal = std_cell ;
margin = m0 ;
nominal = n0 ;
} ;

set index (best,typical,worst) {
Group (INV_X1) = INV_X1 ;
Group (INV_X2) = INV_X2 ;
Group (INV_X3) = INV_X3 ;
Group (INV_X4) = INV_X4 ;
Group (INV_X8) = INV_X8 ;
Group (NAND2_X1) = NAND2_X1 ;
Group (NAND2_X2) = NAND2_X2 ;
Group (NAND2_X4) = NAND2_X4 ;
Group (NOR2_X1) = NOR2_X1 ;
Group (NOR2_X2) = NOR2_X2 ;
Group (NOR2_X4) = NOR2_X4 ;
} ;

-> This is my *.lib File:

library(basic_char) {

delay_model : table_lookup;
in_place_swap_mode : match_footprint;

/* unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1mA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1nW";
capacitive_load_unit (1,pf);

nom_process : 1;
nom_voltage : 1.1;
nom_temperature : 25;
operating_conditions ( typical ) {
process : 1;
voltage : 1.1;
temperature : 25;
}
default_operating_conditions : typical;
define_group(ecsm_waveform, rise_transition);
define_group(ecsm_waveform, fall_transition);
define(ecsm_version, library, float);
define(s-ecsm_version, library, float);
define(ecsm_vtp, library, float);
define(ecsm_vtn, library, float);
define(index_1, ecsm_waveform, string);
define(values, ecsm_waveform, string);
define_group(ecsm_capacitance, rise_transition);
define_group(ecsm_capacitance, fall_transition);
define(threshold_pct, ecsm_capacitance, float);
define(index_1, ecsm_capacitance, string);
define(values, ecsm_capacitance, string);
define_group(ecsm_capacitance, pin);
ecsm_version : 2.0 ;
s-ecsm_version : 1.2 ;
ecsm_vtp : 0.15;
ecsm_vtn : 0.15;

/* -------------------- *
* Design : PM_INV_X1_A *
* -------------------- */
cell (PM_INV_X1_A) {
area : 0.0;
cell_leakage_power : 0;
dont_use : true;
dont_touch : true;
}

/* ---------------------- *
* Design : PM_INV_X1_VDD *
* ---------------------- */
cell (PM_INV_X1_VDD) {
area : 0.0;
cell_leakage_power : 0;
dont_use : true;
dont_touch : true;
}

/* ---------------------- *
* Design : PM_INV_X1_VSS *
* ---------------------- */
cell (PM_INV_X1_VSS) {
area : 0.0;
cell_leakage_power : 0;
dont_use : true;
dont_touch : true;
}

-> This is a part of my netlist spice File:

* File: INV_X1.pex.netlist.pex

.subckt PM_INV_X1_A 2 6 9 14
c10 18 0 0.00705809f
c11 9 0 0.00708646f
c12 6 0 0.0512548f
c13 2 0 0.0362967f
r14 11 18 3.952
r15 9 11 89.3538
r16 9 14 0.137524
r17 5 18 1.98872
r18 5 6 56.94
r19 2 18 40.248
.ends

.subckt PM_INV_X1_ZN 3 7 8
c6 3 0 0.0557277f
r7 7 8 2.208
r8 3 7 1.092
.ends

.subckt PM_INV_X1_VSS 6 9 12 13 16
c9 20 0 0.00822239f
c10 16 0 0.0072739f
c11 15 0 0.00194583f
c12 13 0 0.00894904f
c13 10 0 0.0104102f
c14 9 0 0.00872576f
c15 6 0 0.0159924f
r16 15 16 0.192923
r17 13 15 0.198769
r18 13 20 0.993846
r19 10 12 0.178824
r20 9 20 0.281707
r21 9 12 0.234706
r22 5 10 0.264221
r23 5 6 1.47657
.ends

.subckt PM_INV_X1_VDD 6 9 12 13 16
c9 16 0 0.0092802f
c10 15 0 0.00822239f
c11 13 0 0.00894904f
c12 10 0 0.0103515f
c13 9 0 0.00878269f
c14 6 0 0.0161689f
r15 13 16 0.391692
r16 13 15 0.993846
r17 10 12 0.178824
r18 9 15 0.281707
r19 9 12 0.234706
r20 5 10 0.264221
r21 5 6 0.722
.ends

.subckt INV_X1 A ZN VSS VDD
*
* VDD VDD
* VSS VSS
* ZN ZN
* A A
M_i_0 N_ZN_M_i_0_d N_A_M_i_0_g N_VSS_M_i_0_s N_VSS_M_i_0_b NMOS_VTG L=5e-08
+ W=4.15e-07 AD=4.3575e-14 AS=4.3575e-14 PD=1.04e-06 PS=1.04e-06
M_i_1 N_ZN_M_i_1_d N_A_M_i_1_g N_VDD_M_i_1_s N_VDD_M_i_1_b PMOS_VTG L=5e-08
+ W=6.3e-07 AD=6.615e-14 AS=6.615e-14 PD=1.47e-06 PS=1.47e-06
*

* File: INV_X1.pex.netlist.INV_X1.pxi

x_PM_INV_X1_A N_A_M_i_0_g N_A_M_i_1_g N_A_c_2_p A PM_INV_X1_A
x_PM_INV_X1_ZN N_ZN_M_i_0_d ZN N_ZN_M_i_1_d PM_INV_X1_ZN
x_PM_INV_X1_VSS N_VSS_M_i_0_s N_VSS_c_19_n VSS N_VSS_c_24_p N_VSS_M_i_0_b
+ PM_INV_X1_VSS
x_PM_INV_X1_VDD N_VDD_M_i_1_s N_VDD_c_28_n VDD N_VDD_c_33_n N_VDD_M_i_1_b
+ PM_INV_X1_VDD
cc_1 N_A_M_i_0_g N_ZN_M_i_0_d 0.0251221f
cc_2 N_A_c_2_p N_ZN_M_i_0_d 0.0295357f
cc_3 N_A_M_i_0_g N_VSS_M_i_0_s 0.00684341f
cc_4 N_A_c_2_p N_VSS_M_i_0_s 0.00600317f
cc_5 N_A_M_i_0_g N_VSS_c_19_n 0.00535047f
cc_6 N_A_c_2_p N_VSS_c_19_n 7.09543e-19
cc_7 N_A_M_i_1_g N_VDD_M_i_1_s 0.00684341f
cc_8 N_A_c_2_p N_VDD_M_i_1_s 0.00156891f
cc_9 N_A_M_i_1_g N_VDD_c_28_n 0.00538565f
cc_10 N_A_c_2_p N_VDD_c_28_n 4.52549e-19
cc_11 N_ZN_M_i_0_d N_VSS_M_i_0_s 0.0192548f
cc_12 N_ZN_M_i_0_d N_VSS_c_19_n 0.0227788f
cc_13 N_ZN_M_i_0_d N_VDD_M_i_1_s 0.0192548f
cc_14 N_ZN_M_i_0_d N_VDD_c_28_n 0.0227788f
cc_15 N_VSS_M_i_0_s N_VDD_M_i_1_s 2.92631e-19
cc_16 N_VSS_c_24_p N_VDD_c_33_n 4.69642e-19
cc_17 N_VSS_M_i_0_b N_VDD_M_i_1_b 2.45701e-19

*
.ends
*
*