Generated, gated and multiplexed clocks

Hi guys,

I implemented a module with multiple clock inputs which I need to synthesize.

say I have clk1_in & clk2_in input to a clock mux. The mux output is clk_mux_out. Then clk_mux_out is gated to generate clk_mux_g.

Do I have to define all these clocks in the synthesis script ?

What I do is define all these clocks, assign them the same domain and clock frequency.

In case I want to make the constraint of one of these clocks tighter than others for as margin is it harmful regarding the clock to clock edge ?

In case I multiplex two clock of different frequencies, do I need to constraint the mux output to the fastest clock ?