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Timing analysis Cadence RTL compiler

kenambo

Hi all

I want to do some post synthesis analysis using Cadence RTL compiler to understand the timing concepts.

While doing this i got into a doubt that is what will happen if i define clock only for the clk port and keep other ports undefined like not setting any input or output external delays.

By doing like the above.. how rtl compiler generates timing report and i saw R and F in the timing report of a synthesized design.

What does this R and F stands for?

thanks.

Parents

  • If you do not define a clock or delay, you are leaving for the tool to define, whatever tool you use. I would say that is simply asking for trouble so I would define all the I/O hence not needing to wonder what each tool may do

    just my 2c,

    gh-

Reply

  • If you do not define a clock or delay, you are leaving for the tool to define, whatever tool you use. I would say that is simply asking for trouble so I would define all the I/O hence not needing to wonder what each tool may do

    just my 2c,

    gh-

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