Instance a vhdl module inside a verilog file

Hi everyone,

I want to instance a vhdl module(file) inside a verilog file. I have to do it because my functional view is a vhdl file and their digital test structure was developed in Verilog.

I have the following code:

`include "mux.vhd"
module pulse_controller_dft (

//pin definitions

)

//input definitions

mux   mux7(

.d0 (d0),

.d1 (d1),

.s(s),

.y(y)

);   // vhdl module to instance

// other modules to instance

endmodule

Inside the vhdl file, the name of entity was declared with the same filename of the vhdl.

My idea is synthesize both using an unificated verilog file. However executing a parsing check with ncverilog the following error appears:

pulse_controller_syncreset Ipc(.clk(clk),.rst_n(rst_n),.cmd_disable_n_i(cmd_disable_n_i),.addr_i(addr_i[1:0]),.cmd_enable_n_i(cmd_enable_n_i),.sp_n_i(sp_n_i),.ocp_i(ocp_i),.uvp_i(uvp_i),.otp_i(otp_i),.ohd_i(ohd_i[3:0]),.cmd_o(cmd_o[3:0]),.pulse_o(pulse_o),.double_o(double_o),.false_o(false_o),.fault_o(fault_o),.cmd_disable_o(cmd_disable_o));    
                                 |
ncelab: *E,CUVMUR (../jorge/smdh/rh_drv/frontend/pulse_controller_syncreset/pulse_controller_syncreset_dft.v,80|30): instance 'pulse_controller_dft.Ipc' of design unit 'pulse_controller_syncreset' is unresolved in 'worklib.pulse_controller_dft:v'.
ncverilog: *E,ELBERR: Error during elaboration (status 1), exiting.

Any suggestions?

Thanks