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EDI saveNetlist gives a Verilog netlist with assign statement

xfan

When running saveNetlist in EDI, I got a hierarchical Verilog netlist with assign statement in use! Some nets have the names that are different in the netlist from what I see in the GUI after layout. I have no idea how could this happen.

If I save the netlist without hierarchy, i.e., saveNetlist -flat, then there is no assign statement in the Verilog netlist.

Note that there is no assign statement in the loaded post-synthesis netlist.

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