Clock definition in sdc file

Hello,

In my design I need to distribute the clock signal to 32 different external blocks with minimun delay and skew respect to the clock input source. So in my vhdl I defined:

clk_out(31)<=clk_in;

clk_out(30)<=clk_in;

...

clk_out(0)<=clk_in;

In the sdc file I declare these clocks as follow (for each port):

create_generated_clock -source [get_ports {clk_in}] -name clk_out_0 -divide_by 1 [get_ports {clk_out[0]}]

then I set the output delay for each group of combinatorial outputs that should be related to this clk_out.

set_output_delay -clock clk_out_0 0.2 {a[0] b[0] c[0]}

and so on...

Since the clk_out signals are not used inside my design (I use clk_in for the internal logic), the synthesis report "No paths found" for these signals, and during PnR with Encounter the clock outputs are not distributed with a clock tree, but it is inserted only one buffer for all the 32 outputs, giving then a huge delay on these nets.

Please, does anybody know how to force Encounter to propagate these clock outputs with a clock tree like the internal clk_in?

Regards