Hold violation fixing

i got some problem like this, any have ideas? thanks

I got the answer from another forum. You will get a true status of hold results only after CTS. So it is better we complete CTS and then look at hold results. Assume u have setup violations in your design. You have to resolve it by reducing Tcomb. So 2 options available to u are pipelining and say retiming. Pipelining involves logic changes where you add registers to your RTL (logic changes)
Asume Tskew is 0 for simplicity.. If you have hold violations it means you have to push your data further ahead. You can do that by increasing TComb. The easiest way to do that is to add buffers in the data path. With this you can get incremental and precise control over the delay. If you want to do logic changes to solve this problem, what logic will you add in the data path? Any logic changes proposed will only complicate your problems. On the other hand, to fix set up violations, you have to make your data path faster. You can either upsize your cells or change your logic for this.