How to write sdc for pre/post CTS ?

Hi Kazuhiro-san

(1) If the same clock names isn't defined in other MMMC modes, you can try something like this:

if {[get_property [get_clocks $my_clock] is_propagated_clock]] == "true"} {
            set_clock_uncertainty [expr .......] $my_clock
} else {
            set_clock_uncertainty [expr .......] $my_clock
}

(2) If same clock is present in other MMMC modes, you can use the customized proc "checkClockProp":

Usage: checkClockProp -clock <clock_name>

if {[checkClockProp -clock $my_clock] == "true"} {

            set_clock_uncertainty [expr .......] $my_clock
} else {
            set_clock_uncertainty [expr .......] $my_clock
}

proc checkClockProp {args} {

# Get clock name
if {[regexp {\-clock} $args]} {
set clockName [lindex $args [expr [lsearch $args -clock] + 1]]
}


# Help
set helpString "Usage : checkClockProp -clock <clock_name> -help "

if {[regexp {\-help} $args]} {
puts $helpString
return 0
}

# Main code
#########################################################################


# Check clock name(s)
if {[lsort -u [get_object_name [get_clocks -quiet $clockName]]] == ""} {
puts "\nERROR: Clock $clockName not found!"
return 0
} else {
set clock [lsort -u [get_object_name [get_clocks -quiet $clockName]]]
}

# Check clock propagation
if {![string match "false" [lsort -u [get_property [get_clocks $clock] is_propagated_clock]]]} {
return "true"
} else {
return "false"
}

}

Let me know if you see any issues.

Thanks

Khandaker

Hi Khandaker,

Thank you for your reply.

Unfortunately, it didn't work again. Because I tried to run the following command at EDI command prompt after postCTS timing analysis finished. Aut it seems the clock (my_clk) is not propagated mode.

encounter 4> get_property [get_clocks {my_clk}] is_propagated_clock
false false

But it seems that the timing analysis is successfully done in postCTS mode as shown below. (Header section of tarpt)

#  Command:           timeDesign -postCTS -pathReports -drvReports -slackReports -numPaths 50 -prefix leon_postCTS -outDir timingReports

Is there any restrictions to use this command ?

Hi Kazuhiro-san

I assume you used the valid clock name in the 'my_clock' variable.

get_property [get_clocks ${my_clk}] is_propagated_clock

If the above assumption is true, it looks like the timing analysis was done w/o the propagated clock. BTW, how do you propagate the clocks in the SDC? 

Thanks

Khandaker

Hi Khandaker,

I used and modified the SDC in the RAK package (Introdution to EDI System 13.2 & Block Implementation Flow) so the clock is defined as shown below.

create_clock -name {my_clk} -period 4.000 -waveform { 0.000 2.000 } [list  [get_ports {clk}]]

So I didn't add $ for the clock name.

>BTW, how do you propagate the clocks in the SDC?

Do I need anything to do that in the SDC ? Does it (propagate or not propagate) depend on the option (-preplace, -preCTS or -postCTS ,etc) for the timeDesign command ?

Hi Kazuhiro-san

After building the clock-tree, you need to make sure the clocks are propagated. Please use the following set of the SDC before running the timeDesign:

set_propagated_clock [all_clocks] 

OR

set_propagated_clock [get_clocks my_clock]

Thanks

Khandaker

Hi Khandaker,

I am confused. My original question is to ask how to identify pre/post CTS in the SDC. I have some more questions.

1. If we need the set_propagated_clock command to propagate clock (it means post-CTS), does it mean that the SDC (includes set_propagated_clock) is for post-CTS usage but not for pre-CTS?

2. If we use this command for pre-CTS netlist, is clock propagation really done ?

3. Where should this command be ? (Before or after the following code ?)

if {[get_property [get_clocks $my_clock] is_propagated_clock]] == "true"} {
            set_clock_uncertainty [expr .......] $my_clock
} else {
            set_clock_uncertainty [expr .......] $my_clock
}

Over the decades I have learned to never touch the constraints.
You are far better off temporarily changing your staged clock uncertainty with the setOptMode –drcMargin –setupTargetSlack -holdTargetSlack options.
preCTS –setupTargetSlack +150ps, postCTS–setupTargetSlack +50ps and postRoute –setupTargetSlack +000ps
TimeDesign reports will still be based on the source constraints without the additional user target margins. ( also +slack keeps the boss happy )
We typically reference ip / op delays relative to a virtual clock and rely on clockDesign update_io_latency to accurately adjust the virtual latency.

Source constraints = ideal
create_clock -name RX_CLK -period 1.714 [get_ports i_clk]
set_clock_latency -max 0.400 [get_clocks RX_CLK]
set_clock_latency -min 0.200 [get_clocks RX_CLK]
set_clock_uncertainty -setup 0.200 [get_clocks RX_CLK]
set_clock_uncertainty -hold 0.020 [get_clocks RX_CLK]
create_clock -name RX_CLK_VIRTUAL -period 1.714
set_clock_latency -max 0.400 [get_clocks RX_CLK_VIRTUAL]
set_clock_latency -min 0.200 [get_clocks RX_CLK_VIRTUAL]
set_input_delay -clock [get_clocks RX_CLK_VIRTUAL] -add_delay -max 0.460 [all_inputs]
set_output_delay -clock [get_clocks RX_CLK_VIRTUAL] -add_delay -max 1.280 [all_outputs]

clockDesign update_io_latency propagated and adjusted
create_clock -name RX_CLK -period 1.714 [get_ports i_clk]
set_propagated_clock [get_clocks RX_CLK]
set_clock_uncertainty -setup 0.200 [get_clocks RX_CLK]
set_clock_uncertainty -hold 0.020 [get_clocks RX_CLK]
create_clock -name RX_CLK_VIRTUAL -period 1.714
set_clock_latency -max 0.4562 [get_clocks RX_CLK_VIRTUAL]
set_clock_latency -min 0.2643 [get_clocks RX_CLK_VIRTUAL]
set_input_delay -clock [get_clocks RX_CLK_VIRTUAL] -add_delay -max 0.460 [all_inputs]
set_output_delay -clock [get_clocks RX_CLK_VIRTUAL] -add_delay -max 1.280 [all_outputs]

Shawn

Hi Shawn,

Thank you for your advise. This looks one of the great ideas to do handle margins.

But my original intention of this article is that I want to have only 1 SDC file for all design phases, because we usually did so (IBM Einstimer timing methodology). Don't you think I can do that ? How many SDCs do you generally have ? (pre-CTS, post-CTS, post-Route, etc)

You missed the point completely ... one source to rule them all. ( or as few as possible )
Let the tools take care of the preCTS and postCTS variations for you.
You modify your optimization stage margins within the run script not the constraints.

In the real MMMC world there is rarely just one clock , never one mode and you are guaranteed more than one corner.
You cannot possibly keep track of all the combinations and permutations manually ... Let the tools do the work for you!!

My current very old school 65nm SOC eco has 5 separate clocks, two functional modes and three DFT modes across four corners.
That’s 5 ideal mode constraint source files across 4 corners ... and do the math ... 20 postCTS variants.
Wait till you see the 14nm corners!

As always the K.I.S.S. principal rules supreme ... Let the tools do their job.

Shawn

Hi Shawn,

I am still a bit confused. You showed examples in the last post. Do they mean there are 2 different source files for each pre and post CTS? If so, do you have 10 (5 modes x 2) source files?

>Source constraints = ideal
>create_clock -name RX_CLK -period 1.714 [get_ports i_clk]
>set_clock_latency -max 0.400 [get_clocks RX_CLK]
>set_clock_latency -min 0.200 [get_clocks RX_CLK]
>set_clock_uncertainty -setup 0.200 [get_clocks RX_CLK]
>set_clock_uncertainty -hold 0.020 [get_clocks RX_CLK]
>create_clock -name RX_CLK_VIRTUAL -period 1.714
>set_clock_latency -max 0.400 [get_clocks RX_CLK_VIRTUAL]
>set_clock_latency -min 0.200 [get_clocks RX_CLK_VIRTUAL]
>set_input_delay -clock [get_clocks RX_CLK_VIRTUAL] -add_delay -max 0.460 [all_inputs]
>set_output_delay -clock [get_clocks RX_CLK_VIRTUAL] -add_delay -max 1.280 [all_outputs]

>clockDesign update_io_latency propagated and adjusted
>create_clock -name RX_CLK -period 1.714 [get_ports i_clk]
>set_propagated_clock [get_clocks RX_CLK]
>set_clock_uncertainty -setup 0.200 [get_clocks RX_CLK]
>set_clock_uncertainty -hold 0.020 [get_clocks RX_CLK]
>create_clock -name RX_CLK_VIRTUAL -period 1.714
>set_clock_latency -max 0.4562 [get_clocks RX_CLK_VIRTUAL]
>set_clock_latency -min 0.2643 [get_clocks RX_CLK_VIRTUAL]
>set_input_delay -clock [get_clocks RX_CLK_VIRTUAL] -add_delay -max 0.460 [all_inputs]
>set_output_delay -clock [get_clocks RX_CLK_VIRTUAL] -add_delay -max 1.280 [all_outputs]