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How do DRC violations occur even if we give lef files as design rules?

biju4u90

In digital physical design, how do DRC violations occur even if we give lef files as design rules? In other words, why do the geometry violations like minimum spacing violations occur even though the minimum spacing requirements of metal layers are specified in the lef file?

  • Physically impossible = no legal solution.

    Your rules are in conflict with themselves i.e. min space + min width > pitch.

    Congestion, placeDesign pin density too high i.e. too many connections in a localized area.
    Just because trialRoute completes successfully doesn’t guarantee nanoRoute will.

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