spare, freed, and gate array cell insertion in pre-ECO flow

Hi everyone,

during the implementation of my flow, I take a look to the advanced features of the digital flow.
Thus, I saw the ECO flow and started to understand how to handle it, purely in anticipation because I didn't notice a bug yet.

I red the chapter in the UG plus several topics on the support part and also on this forum.
However, a question remains for me ; it is a basic concept that nobody mentions so I guess that it's obvious, but I hope you'll apologize my lake of reasoning :) :

How do we prepare the ECO flow ?

I mean, before even notice that we have a small bug and we have to rerun the design,
we should insert spare, freed and/or gate-array cells in the design, shouldn't we ?

But how do we insert them ? What are the "best practices" to do that ? Placing those cells in the middle of the logic, and fillers+DCAP around the core ?... ? Is there a command in Encounter 14.2 to do that ?

Thanks in anticipation for your answers,

Best regard,

Sébastien