Can we use generated clocks in clock tree synthesis?

Hi all,

I have a special multi-output clocked cell that is basically a flipflop. But it has an additional output which is combinationally (phase) shifted copy of its input clock. This phase shifted copy (or generated clock) has same frequency and duty cycle as master clock. This clock is something that encounter could produce itself by buffering of the mastering clock.

I was wondering if I can use the output clock of these cells to trigger other flipflops, if the phase shifted copy of the master clock is what's "best". The idea is to reduce load on external clock tree and its fanouts.

However the trick is I want encounter to dynamically choose between these two - the master clock and output clock of one of such cells to trigger some other flipflop ensuring that all the constraints are satisfied.  Is there any provision in encounter that allows me to do this?

Thanks