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How to balance the internal clock signal and the clock output?

Hi guys,

I am now working on the P&R of a design which has several clock output ports. These clock output ports are ones that buffered from the input clock. In Encounter, I hope the tool can automatically balance the rising edges of those clock output ports and the clock pins of internal FFs. I tried several ways, like setting SetIoPinAsSync to YES, however, the results seem not good. So, is there any suggestions about how to implement this in Encounter?

Thanks a lot,

Yuanqing

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