How to avoid "leap frog" situation when generating a long shift register with SOC Encounter?

I have a long shift register that is synthesized with RTL compiler using my customized standard cell. LEF and liberty file is also generated with virtuoso and liberate. (version is ic616 and liberate 14)

Then it is place and routed with soc encounter 14.

in post layout simulation with ultrasim 14, the shift output result shows some difference between extraction level R and RC. specifically, some data is 1 (or several) cycle ahead of the other output data series. 

I suspect this is due to the clock edge arriving time mismatch (jitter) to the clock strobe on the DFFs, so that the leap frog situation occured.

Should there be some sdf constraint to specify a clock tree that would properly drive the long shift register to avoide the described situation?

for example but not limited to:  the clock of (N+1)-th DFF should always come before N-th DFF's.

Anybody has any idea and comment?

Thanks in advance. 

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Kangqiao