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Enabling SI aware CTS and Optimization

Hi All,

I have timing violations because of cross talk in my design at post route stage. All the violations are purely because of cross talk. I want make sure that this is taken care from CTS, post CTSOPT etc.

Is there any way I can make CCOPT cross talk aware??

Regards,

Anil

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sandy2186 over 8 years ago

Hi Kari and All
Kindly let me know which combination of cells (buffer only/ Inverter only/Combo of both) works better for Clock tree synthesis!
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sandy2186 over 8 years ago

Hi Kari and All
Kindly let me know which combination of cells (buffer only/ Inverter only/Combo of both) works better for Clock tree synthesis!
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