Placement Density

Good morning everybody,

I would like to ask a question about the placement desnity and the effective utilization of a digital block designed using standard cells.

During the floorplan I set the core occupation at 0.75 (75%) , after the placement the design experiences few timing violations and the density increases to 80.398%. After the optimization all the timing violations are fixed and the design density increases to 80.709%.

Then I implementend the clock tree synthesis, the post CTS optimization, the routing and the post routing optimization. After the last step I got a density of 82.225% and no timing violations. Also the geometry and the connectivity are ok.

At this point I added the filler cells and the density increases to 107%, the summary report stays that:

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Floorplan/Placement Information
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Total area of Standard cells: 18031.356 um^2  
Total area of Standard cells(Subtracting Physical Cells): 13837.874 um^2  
Total area of Macros: 0.000 um^2  
Total area of Blockages: 0.000 um^2  
Total area of Pad cells: 0.000 um^2  
Total area of Core: 18040.896 um^2  
Total area of Chip: 18642.537 um^2  
Effective Utilization: 1.0714e+00

My question is, does the density above 100% a problem? Why the density increase so much after the filler insertion?

Thank you.