Characterizing header switch for power gating using ELC

Hi,

    I want to synthesize the ISCAS'85 multiplier benchmark circuit with a power gating header p-FinFET switch added. I've built a simple custom standard cell library (2 i/p NAND, NOR and a NOT) to realize this combinational circuit and the .lib was generated by running ELC. I'm supplying my own FinFET models in the logic gates' netlist during the characterization step. ELC gives me the timing-power lookup table for these logic gates as per the non-linear CMOS delay model (NLDM) approach. However, I'm unable to model the header switch in my .lib. My university has access to SAED_90nm EDK from Synopsys and the header switches have been modeled using the Composite Current Source (CCS) approach generated by Liberty NCX tool which takes into account the IR drop during operation by working with current waveforms instead of power-timing lookup tables.

I understand that ELC can generate CCS .lib by specifying EC_CHAR="CCS-TIMING CCS-POWER" in the configuration script. But how should I write the netlist for a header switch so that I can get a header.lib in the CCS format using ELC? Unlike a NAND netlist, which has a pull-up network connected to VDD and pull-down network connected to GND rails for the purpose of characterization, the power switch is a bare FinFET with only a pull-up and the pull-down is going to be the synthesized multiplier circuit. Do I need to insert a resistor that mimics the pull-down load that the power switch will have to drive?

Thank you.

Regards

Arun