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Encounter not routing to WellTap pins using routeDesign or sroute

noza

Hi,

I am trying to use WellTaps to power my substrates to a different bias level because the process we're using is FDSOI, which allows for reverse body biasing.  As such, I've included the following command to my tcl script that sets up the design.

addWellTap -cell Welltap_T16 -cellInterval 40.0 -skipRow 1

When I try to route the design (routeDesign), it routes all of my signal pins, but doesn't connect these pins.  My original assumption was that this could be because it is treating these two nets (the substrate to the NFET and substrate to the PFET) as power layers instead of signal layers.  As such, I have also tried explicitly specifying these two nets (g_2vnsub and g_2vpsub) as power rails and then tried to use sroute to route them to planes on a higher layer.  This also doesn't work.

Can someone guide me through the process of auto-routing substrate connections using welltaps?

As a reference, I have also included the LEF macro for my wellTap below:

MACRO Welltap_T16
  CLASS CORE ;
  ORIGIN 0 0 ;
  FOREIGN Welltap_T16 0 0 ;
  SIZE 0.19 BY 1.55 ;
  SYMMETRY X Y ;
  SITE CoreSite ;
  PIN g_2Vdd
    DIRECTION INOUT ;
    USE POWER ;
    SHAPE ABUTMENT ;
    PORT  
      LAYER M1 ;
        RECT 0 1.475 0.19 1.625 ;
    END   
  END g_2Vdd
  PIN g_2GND
    DIRECTION INOUT ;
    USE GROUND ;
    SHAPE ABUTMENT ;
    PORT  
      LAYER M1 ;
        RECT 0 -0.075 0.19 0.075 ;
    END   
  END g_2GND
  PIN g_2vnsub
    DIRECTION INOUT ;
    USE POWER ;
    SHAPE ABUTMENT ;
    PORT  
      LAYER V1 ;
        RECT 0.07 0.372 0.12 0.422 ;
        RECT 0.07 0.23 0.12 0.28 ;
      LAYER M1 ;
        RECT 0.07 0.185 0.12 0.467 ;
      LAYER M2 ;
        RECT 0.07 0.198 0.12 0.454 ;
    END   
  END g_2vnsub
  PIN g_2vpsub
    DIRECTION INOUT ;
    USE POWER ;
    SHAPE ABUTMENT ;
    PORT  
      LAYER V1 ;
        RECT 0.07 1.27 0.12 1.32 ;
        RECT 0.07 1.128 0.12 1.178 ;
      LAYER M1 ;
        RECT 0.07 1.083 0.12 1.365 ;
      LAYER M2 ;
        RECT 0.07 1.096 0.12 1.352 ;
    END   
  END g_2vpsub
END Welltap_T16


Any help would be much appreciated!

I am using Encounter 14.15.

Hi,

I am trying to use WellTaps to power my substrates to a different bias level because the process we're using is FDSOI, which allows for reverse body biasing.  As such, I've included the following command to my tcl script that sets up the design.

addWellTap -cell Welltap_T16 -cellInterval 40.0 -skipRow 1

When I try to route the design (routeDesign), it routes all of my signal pins, but doesn't connect these pins.  My original assumption was that this could be because it is treating these two nets (the substrate to the NFET and substrate to the PFET) as power layers instead of signal layers.  As such, I have also tried explicitly specifying these two nets (g_2vnsub and g_2vpsub) as power rails and then tried to use sroute to route them to planes on a higher layer.  This also doesn't work.

Can someone guide me through the process of auto-routing substrate connections using welltaps?

As a reference, I have also included the LEF macro for my wellTap below:

MACRO Welltap_T16
  CLASS CORE ;
  ORIGIN 0 0 ;
  FOREIGN Welltap_T16 0 0 ;
  SIZE 0.19 BY 1.55 ;
  SYMMETRY X Y ;
  SITE CoreSite ;
  PIN g_2Vdd
    DIRECTION INOUT ;
    USE POWER ;
    SHAPE ABUTMENT ;
    PORT  
      LAYER M1 ;
        RECT 0 1.475 0.19 1.625 ;
    END   
  END g_2Vdd
  PIN g_2GND
    DIRECTION INOUT ;
    USE GROUND ;
    SHAPE ABUTMENT ;
    PORT  
      LAYER M1 ;
        RECT 0 -0.075 0.19 0.075 ;
    END   
  END g_2GND
  PIN g_2vnsub
    DIRECTION INOUT ;
    USE POWER ;
    SHAPE ABUTMENT ;
    PORT  
      LAYER V1 ;
        RECT 0.07 0.372 0.12 0.422 ;
        RECT 0.07 0.23 0.12 0.28 ;
      LAYER M1 ;
        RECT 0.07 0.185 0.12 0.467 ;
      LAYER M2 ;
        RECT 0.07 0.198 0.12 0.454 ;
    END   
  END g_2vnsub
  PIN g_2vpsub
    DIRECTION INOUT ;
    USE POWER ;
    SHAPE ABUTMENT ;
    PORT  
      LAYER V1 ;
        RECT 0.07 1.27 0.12 1.32 ;
        RECT 0.07 1.128 0.12 1.178 ;
      LAYER M1 ;
        RECT 0.07 1.083 0.12 1.365 ;
      LAYER M2 ;
        RECT 0.07 1.096 0.12 1.352 ;
    END   
  END g_2vpsub
END Welltap_T16


Any help would be much appreciated!

I am using Encounter 14.15.

- See more at: community.cadence.com/.../36036

Hi,

I am trying to use WellTaps to power my substrates to a different bias level because the process we're using is FDSOI, which allows for reverse body biasing.  As such, I've included the following command to my tcl script that sets up the design.

addWellTap -cell Welltap_T16 -cellInterval 40.0 -skipRow 1

When I try to route the design (routeDesign), it routes all of my signal pins, but doesn't connect these pins.  My original assumption was that this could be because it is treating these two nets (the substrate to the NFET and substrate to the PFET) as power layers instead of signal layers.  As such, I have also tried explicitly specifying these two nets (g_2vnsub and g_2vpsub) as power rails and then tried to use sroute to route them to planes on a higher layer.  This also doesn't work.

Can someone guide me through the process of auto-routing substrate connections using welltaps?

As a reference, I have also included the LEF macro for my wellTap below:

MACRO Welltap_T16
  CLASS CORE ;
  ORIGIN 0 0 ;
  FOREIGN Welltap_T16 0 0 ;
  SIZE 0.19 BY 1.55 ;
  SYMMETRY X Y ;
  SITE CoreSite ;
  PIN g_2Vdd
    DIRECTION INOUT ;
    USE POWER ;
    SHAPE ABUTMENT ;
    PORT  
      LAYER M1 ;
        RECT 0 1.475 0.19 1.625 ;
    END   
  END g_2Vdd
  PIN g_2GND
    DIRECTION INOUT ;
    USE GROUND ;
    SHAPE ABUTMENT ;
    PORT  
      LAYER M1 ;
        RECT 0 -0.075 0.19 0.075 ;
    END   
  END g_2GND
  PIN g_2vnsub
    DIRECTION INOUT ;
    USE POWER ;
    SHAPE ABUTMENT ;
    PORT  
      LAYER V1 ;
        RECT 0.07 0.372 0.12 0.422 ;
        RECT 0.07 0.23 0.12 0.28 ;
      LAYER M1 ;
        RECT 0.07 0.185 0.12 0.467 ;
      LAYER M2 ;
        RECT 0.07 0.198 0.12 0.454 ;
    END   
  END g_2vnsub
  PIN g_2vpsub
    DIRECTION INOUT ;
    USE POWER ;
    SHAPE ABUTMENT ;
    PORT  
      LAYER V1 ;
        RECT 0.07 1.27 0.12 1.32 ;
        RECT 0.07 1.128 0.12 1.178 ;
      LAYER M1 ;
        RECT 0.07 1.083 0.12 1.365 ;
      LAYER M2 ;
        RECT 0.07 1.096 0.12 1.352 ;
    END   
  END g_2vpsub
END Welltap_T16


Any help would be much appreciated!

I am using Encounter 14.15.

- See more at: community.cadence.com/.../36036

  • I was able to solve this issue by using a feature of the addStripe command, where it automatically routes over PGPins (Power/Ground pins).  Therefore, b/c I designated my substrates as power rails, it was able to add a power stripe over these pins.  Encounter was then automatically able to add the vias from the higher power rail(stripe) down to the pins of my well taps.  The command I used looks something like the following:

    addStripe -nets {g_2vpsub} -direction horizontal -layer M6 -width pin_width -spacing 2 -over_pins 1 -master Welltap_T16

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