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  3. Virtuoso is not importing wire-patches/rectangles defined...

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Virtuoso is not importing wire-patches/rectangles defined in DEF 5.8 file

noza
noza over 9 years ago

Hello Cadence Friends/Experts,

I am facing an unexpected problem where something defined as specified in the LEF/DEF 5.8 Language Reference documentation, doesn't import into Virtuoso (version IC6.1.6-64b-500.11) properly.  Hopefully, I have included all the pertinent information so that one of you might be able to reproduce this problem and help me understand how to fix the problem.

I am using Encounter to route my traces for a large cell and then exporting the output of that Encounter layout as a DEF file.  Encounter creates wire-patches in order to fill in notches that would normally not meet the minimum spacing requirements.  These wire-patches aren't being imported into Virtuoso despite being specified in the DEF file, as rectangles according to the LEF/DEF 5.8 Language Reference. 

I have created a dummy test DEF file to test exactly what is written in the language reference, in Example 4-12.  I have included a screenshot of this portion of the PDF for your convenience below.

I have implemented this basic routing net as specified in my DEF File below (with scaled dimensions), with the hope of creating a rectangle in Virtuoso:

###############################################################
#  Generated by:      Cadence Encounter 14.15-s029_1
#  OS:                Linux x86_64(Host ID XXXXXXX)
#  Generated on:      Mon Jul 25 11:58:48 2016
#  Design:            fooDesign    
#  Command:           defOut -netlist -routing foo58.def
###############################################################
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN fooDesign ;
UNITS DISTANCE MICRONS 1000 ;

PROPERTYDEFINITIONS
    COMPONENTPIN designRuleWidth REAL ;
    DESIGN FE_CORE_BOX_LL_X REAL 0.000 ;
    DESIGN FE_CORE_BOX_UR_X REAL 10.000 ;
    DESIGN FE_CORE_BOX_LL_Y REAL 0.000 ;
    DESIGN FE_CORE_BOX_UR_Y REAL 10.000 ;
END PROPERTYDEFINITIONS

DIEAREA ( 0 0 ) ( 10000 10000 ) ;

# SPECIALNETS 1 ;
# - fooPin
#
#  + RECT M1 ( 4000 1000 ) ( 6000 3000 )
#  ;
# END SPECIALNETS

NETS 1 ;
- fooNet
  + ROUTED M1 ( 0 0 ) ( 5000 0 ) VIRTUAL ( 7000 1000 ) RECT ( -3000 0 -1000 2000 ) ( 7000 7000 )
 ;
END NETS

END DESIGN

When I import this file into Virtuoso, I get the following routing, which doesn't include the rectangle defined by RECT ( -3000 0 -1000 2000), which is contrary to the info in the LEF/DEF Language Reference.  As you can see, it only routes the wires from (0,0) to (5000,0) and (7000,1000) to (7000,7000).  For reference, the green square is a 10um x10um bounding box.  The units in the LEF file are in units of nm, hence the 1000 to represent 1um.

Any ideas about why drawing wire-patches/rectangles isn't working for importing DEF 5.8 into Virtuoso? 


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