Conflict between bus notation in Verilog ('[ ]') and Cadence ('< >')

I'm having an issue arising from the difference in bus notation between Verilog language and Cadence tools.

I have two leafs cells comprising of a structural System Verilog netlist and corresponding layout that were generated by Synopsys PnR tools for a digital implementation using standard cells. I imported the DEF file from the PnR output to generate the layout of the leaf cells and ran the LVS with the corresponding Verilog netlist. To pass LVS, I had to rename the bus terminal names in the layout containing angular brackets '< >' to match the terminal names in Verilog containing square brackets '[ ]'. If I don't take this step, then LVS reports that the pin names in the layout don't match those in the schematic. 

I generated the symbols of the leaf cells using the behavioral System Verilog netlist that was used for synthesis. These generated symbols use the angular bracket for bus notation. 

Then I take those leaf cells and interconnect them in a top level schematic and generate the layout using Generate from Source in Layout XL. The problem now is that Layout XL does not 'see' connectivity of the busses that are connected between the two cells because in the layout the terminals have the square bracket notation (to pass LVS). The following info message occurs:

INFO (LX-1013): Instance terminal 'bus_name<0>' is missing from layout instance '|leaf_cell_name'.

How should I proceed in this situation? I know that one possible solution is to import the verilog netlist into a schematic which will have all the bus terminals with angular brackets, then the LVS issues will be solved. But unfortunately due to a bug in Cadence when importing verilog with global signals https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000tldEEAQ&pageName=ArticleContent&sq=005d0000001T5WTAA0_20161216101036437 , I cannot use this option because I don't have write access to the standard cell libraries at the moment.