Understanding Innovus' hold analysis in a hierarchical design flow utilizing hard macros

Hello,

I have got a problem with generating a hard macro and/or using this hard macro utilizing Cadence Innovus 15.2.
The problem concerns the hold timing analysis of a top design which uses the previously generated hard macro.

The following example depicts this issue and shows a hold analysis for one exemplary path.
This path starts in the top design and ends within the hard macro.

The hold analysis of the sub macro gives the following results:
Other End Arrival Time 0.280
+ Hold                            0.030
+ Phase Shift                 0.000
- CPPR Adjustment      0.000
= Required Time           0.310
  Arrival Time                0.315
  Slack Time                   0.005

The hold analysis of the top design gives the following results:
Other End Arrival Time 0.353
+ Hold                             -0.024
+ Phase Shift                   0.000
- CPPR Adjustment        0.000
= Required Time             0.328
  Arrival Time                  0.339
  Slack Time                     0.010

Both hold analysis are MET (for the tool).
But I am not sure why the hold time for the pin of the sub macro is assumed to be -0.024 in the analysis of the top design.
Related to hold analysis of the sub macro, the hold time for the pin should be -0.005 (what I think).

The following picture gives an better overview of the delays for the path and the related clock within the different macro layers.
So in my opinion the hold check fails here, because 0.654 - 0.633 = 0.021, which is smaller 0.030 (hold time of the register).
This is what gatelevel simulation shows as well (hold violations).



Both, hold analysis and export of the Liberty file for the macro is done in hold view.

Here an extract of the significant innovus commands:

Generate hold view:
create_library_set -name best_library_set -timing "$MIN_TIMELIB"
create_delay_corner -name dc_hold -library_set {best_library_set}
create_analysis_view -name v_hold -constraint_mode {m_hold} -delay_corner {dc_hold}

Do hold timing analysis:
setAnalysisMode -analysisType onChipVariation -cppr both
timeDesign -postRoute -hold -pathReports

Export liberty file:
set_analysis_view -setup v_hold -hold v_hold
do_extract_model -lib_name sub_macro_hold -view v_hold sub_macro_hold.lib

Afterwards the generated liberty file is added to MIN_TIMELIB for the run of the top design

Any suggestions, what I am doing wrong?