Stats

Locked Locked
Replies 0
Subscribers 91
Views 12749
Members are here 0

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Manual modification on layout generated by SoC encounter

Hello,

I have a layout design in SoC encounter to which I want to add manually some extra wires to the layout (these are EXTRA and don't have anything to do with the design netlist) and modify the gap between another some wires (to measure coupling capacitance and crosstalk effects between wires). I'm using NanGate 45nm Open Cell Library.

I'm beginning my design using LEF files.

My questions are:

- Can I do this modification in SoC encounter or I have to go for Virtuoso ?

- If Virtuoso, what is the best format to export my design (GDS or OA) ? and how ? (Please provide detailed description)

- I want to know if there is a difference between parasitic extraction in Virtuoso and encounter. (Which is better in analyzing coupling capacitance between interconnect wires) ?

Thanks

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.