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Calibre LVS errors for a design generated in Encounter

oAwad

Hello all,

 I made a design in SoC Encounter using NangateOpenCellLibrary 45nm. The layout had zero geometry and connectivity violations. I then needed to go to Calibre for LVS and PEX in order to do post-layout simulations, so I did the following in Encounter:

1) Design > Save > GDS/OASIS, then I provided the map file and merged library gds file that came with PDK "NangateOpenCellLibrary.gds" and didn't select "Uniquify cell names"....then finally hit Ok.

2)Design > Save > Netlist,  and I selected the two options in the window and hit Ok.

Then for Calibre part:

1) I run "v2lvs" command to generate spice netlist for LVS

2) I then run LVS using Calibre -gui

In LVS transcript window, I get tons of these two warnings: 

 Open circuit - Same name on different nets:

 Top level port name "KEXP0/n2089" at location (3.515,165.69) on net 2 not valid for netlisting; net id used instead.

(I think the above warning is the reason of the errors)

and in the LVS report I get these:

Error: Different numbers of ports (see below).
Error: Different numbers of nets (see below).
Error: Different numbers of instances (see below).
Error: Connectivity errors.
Error: Property errors.
Warning: Unbalanced smashed mosfets were matched.
Warning: Ambiguity points were found and resolved arbitrarily.
Warning: LVS property resolution maximum exceeded.


NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------

Layout   Source    Component Type

------       ------      -------------

Ports: 12065       35        *

Nets:  29877   29720      *

Instances: 1265 1261      * MN (4 pins)
                  790 790         MP (4 pins)
                  5781   0          * _invb (6 pins)
                 10551 16326   * _invv (4 pins)

(If you added instance "_invb" and "_invv" in both layout and source, they have the same total)

I don't have experience to debug these errors, so can anyone tell me how to debug them ? 

 

  • In Encounter, when I run this command "saveNetlist design.v -phys"
    I get this warning: No Power/Ground connections in top module (design).

    Pwr name (VDD).
    Gnd name (VSS).
    1 Pwr names and 1 Gnd names.
    Creating all pg connections for top cell (design).


    Can this be related to the LVS problem ?

  • "same name on different nets" means that you have an open. the net in question has two pieces that do not connect together. Is this intended? If so, you can either ignore the warning or use a virtual connect. it's hard to debug the other things without having the design.
  • Yes, this can very likely be causing your LVS issues. Did you use the globalNetConnect command to say that your std cell pwr/gnd pins are connected to VDD/VSS? If not, these connections will not be written out in the physical verilog.
  • No it was not intended. But, how on earth I have open circuit and the layout has no geometry and connectivity violations in Encounter ? Moreover, do I need to re-run the whole flow again or there is an easier way to fix it ?

    If there is an easier way than re-running the flow, please tell some hints on how to debug these issues as I don't have much experience.

    Thanks
  • yes, I used globalNetConnect in GUI.
    Connection list:
    VDD:PIN:*.VDD:Module()
    VSS:PIN:*.VSS:Module()

    Should I have tied VDD to high and VSS to low ?
  • I don't use the gui for globalNetConnect, I use the commands. Something like:

    globalNetConnect VSS -type pgpin -pin VSS -all -override -verbose
    globalNetConnect VSS -type tielo -all -override -verbose
    globalNetConnect VDD -type pgpin -pin VDD -all -override -verbose
    globalNetConnect VDD -type tiehi -all -override -verbose

    Is the net that LVS says is open, a pwr/gnd net or a signal net? Do you have a pwr/gnd grid that actually connects all the cells together?

    Also, I haven't used Calibre for years, so I may not be leading you down the right path to solve this. Or it could be some other issue that makes it look like that net is open - really hard to tell without being able to poke around in the design.
  • Thank you Kari

    I would like to know how to check if all std cells pins are connected, how to do that ?

    I think connectivity violations check doesn't check power/ground connections of std cells, does it ?
  • verifyConnectivity will check all the nets, but I'm not sure how it handles the pwr/gnd of std cells. LVS will tell you for sure if a std cell is not connected to pwr/gnd.

  • While the GUI has a "Check" button to find the missing Global Net Connection (GNC), the GUI cannot be used in tcl mode.

    Here is a script to find the missing GNC:

    ============= missing_GNC.tcl =================
    set gncCheck [open GNCCheck.rpt w]
    foreach inst [dbGet top.insts] {
      foreach pgCellTermName [dbGet $inst.pgCellTerms.name] pgTermNetName [dbGet $inst.pgTermNets.name] {
        if {$pgTermNetName eq 0x0} {
          puts $gncCheck "[dbGet $inst.name] Term $pgCellTermName does not have p/g connection"
        }
      }
    }
    close $gncCheck

    ======================================

    Example:

    innovus > source missing_GNC.tcl

    After running the scripts, the tool gives all the missing global net connect information in the "GNCCheck.rpt" file as shown here:

    ============================================
    DTMF_INST/i_10048 Term VSS does not have p/g connection
    DTMF_INST/PLLCLK_INST Term vdd! does not have p/g connection
    DTMF_INST/RAM_128x16_TEST_INST/i_10074 Term VSS does not have p/g connection
    DTMF_INST/RAM_128x16_TEST_INST/i_14 Term VSS does not have p/g connection
    DTMF_INST/RAM_128x16_TEST_INST/i_13 Term VSS does not have p/g connection
    DTMF_INST/RAM_128x16_TEST_INST/i_12 Term VSS does not have p/g connection
    DTMF_INST/RAM_128x16_TEST_INST/i_11 Term VSS does not have p/g connection
    =============================================

  • that will show if the pin is assigned a connection, but will not show if that connection has actually been made

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