Cadence RTLCompiler, how to prevent re-synthesis of the same module

Hi ,

Say, in my top level verilog netlist i have a decoder module and it instantiates four instances of the same module DECODER. 

After RTLCompiler has done elaborate and synthesis, they becomes instances of four differently-named modules, DECODER, DECODER_1667, DECODER_1668, and DECODER_1669 and each one has a different logic gate implementation.

How do I prevent the same module been renamed and re-synthesized to different implementations? 

Later in hierarchical P&R, how do i handle this?  do I need to make one of the four copies as master partition, what is the command to make the other three into clones of the master partition?

can someone provide me a solution to this asap ...