I have special devices that similar to vias lie between two metal layers (think about a metal-insulator-metal capacitor, a metal-to-metal fuse, or a component similar to that). The device is completely on metal layers so it can and should be placed on top of cells but it has blockages and pins that need to be considered.
Is there a flow for having the place and route engine place these elements and route them automatically. I have tried the following approach with no luck:
I created the cell in Virtuoso and got the abstract generator to give me a LEF file for it. Then I played with the LEF macro type (block, cover, bump, etc.). Then used the automatic floorplanning capabilities in Encounter to place the Macros across the design and then routed them. I went through all sorts of placement and LEF cell variations none seemed to give me good results (placing the macros on top of each other ignoring the blockage, or placing them without considering proximity, or placing them outside the core boundaries).
I can't help but think that there is a standard flow for placing and routing such elements. Perhaps defining CustomVias? The device is very similar to a Via but it has to be inserted in the netslist as a cell rather than some technology construct. Any help will be appreciated.